72 lines
2.2 KiB
Systemverilog
72 lines
2.2 KiB
Systemverilog
// sim/fp_mult_tb.sv
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`timescale 1ns/1ps
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module fp_mult_tb;
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logic [31:0] a, b, z;
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logic [2:0] rnd;
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logic [7:0] status;
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logic clk = 0, rst = 0;
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// DUT
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fp_mult dut (
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.a(a),
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.b(b),
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.rnd(rnd),
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.z(z),
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.status(status),
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.clk(clk),
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.rst(rst)
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);
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// Clock generation
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always #5 clk = ~clk;
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typedef struct {
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logic [31:0] a;
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logic [31:0] b;
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logic [31:0] expected;
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string desc;
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} test_vector_t;
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test_vector_t tests [11];
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initial begin
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$display("Starting fp_mult test...\n");
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// Normal multiplication cases
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tests[0] = '{32'h3f800000, 32'h40000000, 32'h40400000, "1.0 * 2.0 = 2.0"};
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tests[1] = '{32'h40400000, 32'h40400000, 32'h40c00000, "3.0 * 3.0 = 9.0"};
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tests[2] = '{32'hbf800000, 32'h40000000, 32'hc0400000, "-1.0 * 2.0 = -2.0"};
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tests[3] = '{32'h3f000000, 32'h3f000000, 32'h3e800000, "0.5 * 0.5 = 0.25"};
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tests[4] = '{32'h3f800000, 32'h00000000, 32'h00000000, "1.0 * 0.0 = 0.0"};
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// Corner cases (some may fail if not handled yet)
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tests[5] = '{32'h7f800000, 32'h3f800000, 32'h7f800000, "inf * 1.0 = inf"};
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tests[6] = '{32'hff800000, 32'h3f800000, 32'hff800000, "-inf * 1.0 = -inf"};
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tests[7] = '{32'h7fc00000, 32'h3f800000, 32'h7fc00000, "NaN * 1.0 = NaN"};
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tests[8] = '{32'h00800000, 32'h00800000, 32'h00000000, "denorm * denorm = underflow"};
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tests[9] = '{32'h7f7fffff, 32'h7f7fffff, 32'h7f800000, "max * max = inf (overflow)"};
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tests[10] = '{32'h00000000, 32'hff800000, 32'hffc00000, "0.0 * -inf = NaN"};
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rnd = 3'b000; // default round to nearest
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rst = 1; #10;
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rst = 0; #10;
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for (int i = 0; i < 11; i++) begin
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a = tests[i].a;
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b = tests[i].b;
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#20;
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$display("[%0d] %s", i+1, tests[i].desc);
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$display(" A=%h B=%h => Z=%h (expected %h) %s\n",
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a, b, z, tests[i].expected,
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(z === tests[i].expected) ? "PASS" : "FAIL");
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end
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$display("\nFinished fp_mult test.");
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$stop;
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end
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endmodule
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