// sim/fp_mult_tb.sv `timescale 1ns/1ps module fp_mult_tb; logic [31:0] a, b, z; logic [2:0] rnd; logic [7:0] status; logic clk = 0, rst = 0; // DUT fp_mult dut ( .a(a), .b(b), .rnd(rnd), .z(z), .status(status), .clk(clk), .rst(rst) ); // Clock generation always #5 clk = ~clk; typedef struct { logic [31:0] a; logic [31:0] b; logic [31:0] expected; string desc; } test_vector_t; test_vector_t tests [11]; initial begin $display("Starting fp_mult test...\n"); // Normal multiplication cases tests[0] = '{32'h3f800000, 32'h40000000, 32'h40400000, "1.0 * 2.0 = 2.0"}; tests[1] = '{32'h40400000, 32'h40400000, 32'h40c00000, "3.0 * 3.0 = 9.0"}; tests[2] = '{32'hbf800000, 32'h40000000, 32'hc0400000, "-1.0 * 2.0 = -2.0"}; tests[3] = '{32'h3f000000, 32'h3f000000, 32'h3e800000, "0.5 * 0.5 = 0.25"}; tests[4] = '{32'h3f800000, 32'h00000000, 32'h00000000, "1.0 * 0.0 = 0.0"}; // Corner cases (some may fail if not handled yet) tests[5] = '{32'h7f800000, 32'h3f800000, 32'h7f800000, "inf * 1.0 = inf"}; tests[6] = '{32'hff800000, 32'h3f800000, 32'hff800000, "-inf * 1.0 = -inf"}; tests[7] = '{32'h7fc00000, 32'h3f800000, 32'h7fc00000, "NaN * 1.0 = NaN"}; tests[8] = '{32'h00800000, 32'h00800000, 32'h00000000, "denorm * denorm = underflow"}; tests[9] = '{32'h7f7fffff, 32'h7f7fffff, 32'h7f800000, "max * max = inf (overflow)"}; tests[10] = '{32'h00000000, 32'hff800000, 32'hffc00000, "0.0 * -inf = NaN"}; rnd = 3'b000; // default round to nearest rst = 1; #10; rst = 0; #10; for (int i = 0; i < 11; i++) begin a = tests[i].a; b = tests[i].b; #20; $display("[%0d] %s", i+1, tests[i].desc); $display(" A=%h B=%h => Z=%h (expected %h) %s\n", a, b, z, tests[i].expected, (z === tests[i].expected) ? "PASS" : "FAIL"); end $display("\nFinished fp_mult test."); $stop; end endmodule