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HWDigSys-II
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Christos Choutouridis
c56dea1506
New normalize and round modules
2025-06-13 23:17:18 +03:00
Compulsory coursework-2025-20250609
Init commit
2025-06-09 22:46:39 +03:00
sim
New normalize and round modules
2025-06-13 23:17:18 +03:00
src
New normalize and round modules
2025-06-13 23:17:18 +03:00
.gitignore
Init commit
2025-06-09 22:46:39 +03:00
fp_mult_top.sv
Init commit
2025-06-09 22:46:39 +03:00
fpu_mult.mpf
New normalize and round modules
2025-06-13 23:17:18 +03:00
lab_coursework_2025.pdf
Init commit
2025-06-09 22:46:39 +03:00
Description
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4.1
MiB
Languages
SystemVerilog
65%
TeX
35%