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@@ -74,12 +74,18 @@ namespace utl { |
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private:
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//! \name SPI implementation specific functions
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//!@{
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template <spi::cpol C =CPOL> constexpr bool clkHigh () { return !static_cast<bool>(C); }
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template <spi::cpol C =CPOL> constexpr bool clkLow () { return static_cast<bool>(C); }
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template <spi::bitOrder B =BitOrder> constexpr
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use_if_t <(B == spi::bitOrder::LSB_First), void> shift (byte_t& b) { b <<=1; }
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template <spi::bitOrder B =BitOrder> constexpr
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use_if_t <(B == spi::bitOrder::MSB_First), void> shift (byte_t& b) { b >>=1; }
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template <spi::cpol C =CPOL> static constexpr bool clkHigh () {
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return !static_cast<bool>(C);
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}
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template <spi::cpol C =CPOL> static constexpr bool clkLow () {
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return static_cast<bool>(C);
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}
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static constexpr bool clkH_ {clkHigh()};
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static constexpr bool clkL_ {clkLow()};
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//!}
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/*!
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@@ -110,9 +116,13 @@ namespace utl { |
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use_if_t <(C == spi::cpha::LOW), byte_t> _tx_data_impl (byte_t out);
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template <spi::cpha C =CPHA>
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use_if_t <(C == spi::cpha::HIGH), byte_t> _tx_data_impl (byte_t out);
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//!@}
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//! Data members
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//! @{
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private:
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uint32_t nsec_; //!< half period of SPI bus
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//!@}
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//! @}
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};
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/*!
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@@ -127,14 +137,14 @@ namespace utl { |
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use_if_t <(C == spi::cpha::LOW), byte_t>
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spi_bb_i<impl_t, CPOL, CPHA, BitOrder>::_tx_data_impl (byte_t out) {
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byte_t in {};
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SCLK (clkLow());
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SCLK (clkL_);
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for (uint8_t bit {static_cast<uint8_t>(BitOrder)} ; bit ; shift (bit)) {
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MOSI (out & bit); // Out at preceding clock trailing edge
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delay (nsec_); // Half cycle delay
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SCLK (clkHigh()); // Leading edge
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SCLK (clkH_); // Leading edge
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in |= (MISO ()) ? bit : 0; // In at leading clock edge
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delay (nsec_); // Half cycle delay
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SCLK (clkLow()); // Trailing edge
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SCLK (clkL_); // Trailing edge
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}
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return in;
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}
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@@ -151,13 +161,13 @@ namespace utl { |
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use_if_t <(C == spi::cpha::HIGH), byte_t>
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spi_bb_i<impl_t, CPOL, CPHA, BitOrder>::_tx_data_impl (byte_t out) {
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byte_t in {};
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SCLK (clkLow());
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SCLK (clkL_);
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for (uint8_t bit {static_cast<uint8_t>(BitOrder)} ; bit ; shift (bit)) {
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delay (nsec_); // Half cycle delay
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SCLK (clkHigh()); // Leading edge
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SCLK (clkH_); // Leading edge
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MOSI (out & bit); // Out at leading clock edge
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delay (nsec_); // Half cycle delay
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SCLK (clkLow()); // Trailing edge
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SCLK (clkL_); // Trailing edge
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in |= (MISO ()) ? bit : 0; // In at trailing clock edge
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}
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return in;
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@@ -196,12 +206,18 @@ namespace utl { |
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private:
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//! \name SPI implementation specific functions
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//!@{
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template <spi::cpol C =CPOL> constexpr bool clkHigh () { return !static_cast<bool>(C); }
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template <spi::cpol C =CPOL> constexpr bool clkLow () { return static_cast<bool>(C); }
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template <spi::bitOrder B =BitOrder> constexpr
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use_if_t <(B == spi::bitOrder::LSB_First), void> shift (byte_t& b) { b <<=1; }
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template <spi::bitOrder B =BitOrder> constexpr
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use_if_t <(B == spi::bitOrder::MSB_First), void> shift (byte_t& b) { b >>=1; }
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template <spi::cpol C =CPOL> static constexpr bool clkHigh () {
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return !static_cast<bool>(C);
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}
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template <spi::cpol C =CPOL> static constexpr bool clkLow () {
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return static_cast<bool>(C);
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}
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static constexpr bool clkH_ {clkHigh()};
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static constexpr bool clkL_ {clkLow()};
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//!}
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@@ -228,9 +244,13 @@ namespace utl { |
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use_if_t <(C == spi::cpha::LOW), byte_t> _tx_data_impl (byte_t out);
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template <spi::cpha C =CPHA>
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use_if_t <(C == spi::cpha::HIGH), byte_t> _tx_data_impl (byte_t out);
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//!@}
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//! Data members
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//! @{
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private:
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uint32_t nsec_; //!< half period of SPI bus
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//!@}
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//! @}
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};
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/*!
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@@ -245,14 +265,14 @@ namespace utl { |
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use_if_t <(C == spi::cpha::LOW), byte_t>
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spi_bb_i<virtual_tag, CPOL, CPHA, BitOrder>::_tx_data_impl (byte_t out) {
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byte_t in {};
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SCLK (clkLow());
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SCLK (clkL_);
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for (uint8_t bit {static_cast<uint8_t>(BitOrder)} ; bit ; shift (bit)) {
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MOSI (out & bit); // Out at preceding clock trailing edge
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delay (nsec_); // Half cycle delay
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SCLK (clkHigh()); // Leading edge
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SCLK (clkH_); // Leading edge
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in |= (MISO ()) ? bit : 0; // In at leading clock edge
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delay (nsec_); // Half cycle delay
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SCLK (clkLow()); // Trailing edge
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SCLK (clkL_); // Trailing edge
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}
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return in;
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}
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@@ -269,13 +289,13 @@ namespace utl { |
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use_if_t <(C == spi::cpha::HIGH), byte_t>
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spi_bb_i<virtual_tag, CPOL, CPHA, BitOrder>::_tx_data_impl (byte_t out) {
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byte_t in {};
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SCLK (clkLow());
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SCLK (clkL_);
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for (uint8_t bit {static_cast<uint8_t>(BitOrder)} ; bit ; shift (bit)) {
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delay (nsec_); // Half cycle delay
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SCLK (clkHigh()); // Leading edge
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SCLK (clkH_); // Leading edge
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MOSI (out & bit); // Out at leading clock edge
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delay (nsec_); // Half cycle delay
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SCLK (clkLow()); // Trailing edge
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SCLK (clkL_); // Trailing edge
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in |= (MISO ()) ? bit : 0; // In at trailing clock edge
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}
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return in;
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