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HWDigSys-II
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hoo2
1ea7c01bb8
A No-Pipeline version of fp_mult w/o top test bench
2025-06-15 15:58:59 +03:00
Compulsory coursework-2025-20250609
Init commit
2025-06-09 22:46:39 +03:00
sim
A No-Pipeline version of fp_mult w/o top test bench
2025-06-15 15:58:59 +03:00
src
A No-Pipeline version of fp_mult w/o top test bench
2025-06-15 15:58:59 +03:00
.gitignore
Init commit
2025-06-09 22:46:39 +03:00
fp_mult_top.sv
Init commit
2025-06-09 22:46:39 +03:00
fpu_mult.mpf
A No-Pipeline version of fp_mult w/o top test bench
2025-06-15 15:58:59 +03:00
lab_coursework_2025.pdf
Init commit
2025-06-09 22:46:39 +03:00
S
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4.1
MiB
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SystemVerilog
65%
TeX
35%
