Micro template library A library for building device drivers
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classutl_1_1__1wire__uart__i.tex 6.6 KiB

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  1. \hypertarget{classutl_1_1__1wire__uart__i}{}\section{utl\+:\+:\+\_\+1wire\+\_\+uart\+\_\+i$<$ Impl\+\_\+t $>$ Class Template Reference}
  2. \label{classutl_1_1__1wire__uart__i}\index{utl\+::\+\_\+1wire\+\_\+uart\+\_\+i$<$ Impl\+\_\+t $>$@{utl\+::\+\_\+1wire\+\_\+uart\+\_\+i$<$ Impl\+\_\+t $>$}}
  3. 1-\/wire U\+A\+RT interface template class using C\+R\+TP Using the private virtual interface we provide the interface from \+\_\+1wire\+\_\+i$<$$>$
  4. {\ttfamily \#include $<$\+\_\+1wire\+\_\+uart.\+h$>$}
  5. Inheritance diagram for utl\+:\+:\+\_\+1wire\+\_\+uart\+\_\+i$<$ Impl\+\_\+t $>$\+:\begin{figure}[H]
  6. \begin{center}
  7. \leavevmode
  8. \includegraphics[height=3.000000cm]{classutl_1_1__1wire__uart__i}
  9. \end{center}
  10. \end{figure}
  11. \subsection*{Public Types}
  12. \begin{DoxyCompactItemize}
  13. \item
  14. using \mbox{\hyperlink{classutl_1_1__1wire__uart__i_acc885c6ec2395ad20409b01aa4d5f546}{type}} = \mbox{\hyperlink{classutl_1_1__1wire__uart__i}{\+\_\+1wire\+\_\+uart\+\_\+i}}$<$ Impl\+\_\+t $>$
  15. \begin{DoxyCompactList}\small\item\em Export type as identity meta-\/function. \end{DoxyCompactList}\item
  16. using \mbox{\hyperlink{classutl_1_1__1wire__uart__i_acc4364e3aa029405a9b2b25e1fea83ac}{Speed}} = typename \mbox{\hyperlink{classutl_1_1__1wire__i}{\+\_\+1wire\+\_\+i}}$<$ \mbox{\hyperlink{classutl_1_1__1wire__uart__i_acc885c6ec2395ad20409b01aa4d5f546}{type}} $>$\+::\mbox{\hyperlink{classutl_1_1__1wire__uart__i_acc4364e3aa029405a9b2b25e1fea83ac}{Speed}}
  17. \begin{DoxyCompactList}\small\item\em Bring bus speed. \end{DoxyCompactList}\end{DoxyCompactItemize}
  18. \subsection*{Protected Member Functions}
  19. \begin{Indent}\textbf{ Object lifetime}\par
  20. \begin{DoxyCompactItemize}
  21. \item
  22. \mbox{\hyperlink{classutl_1_1__1wire__uart__i_ae14ed1ce068d5601c5623c410a0dbc0c}{\+\_\+1wire\+\_\+uart\+\_\+i}} ()=default
  23. \begin{DoxyCompactList}\small\item\em Allow constructor from derived only. \end{DoxyCompactList}\item
  24. \mbox{\hyperlink{classutl_1_1__1wire__uart__i_afe64da15b5eaf61cd54f357f3ea8b3ea}{$\sim$\+\_\+1wire\+\_\+uart\+\_\+i}} ()=default
  25. \end{DoxyCompactItemize}
  26. \end{Indent}
  27. \subsection*{Additional Inherited Members}
  28. \subsection{Detailed Description}
  29. \subsubsection*{template$<$typename Impl\+\_\+t$>$\newline
  30. class utl\+::\+\_\+1wire\+\_\+uart\+\_\+i$<$ Impl\+\_\+t $>$}
  31. 1-\/wire U\+A\+RT interface template class using C\+R\+TP Using the private virtual interface we provide the interface from \+\_\+1wire\+\_\+i$<$$>$
  32. A 1-\/wire implementation using a microprocessor\textquotesingle{}s uart for bit timing inherited from \mbox{\hyperlink{classutl_1_1__1wire__i}{\+\_\+1wire\+\_\+i}} base class. \begin{DoxySeeAlso}{See also}
  33. \mbox{\hyperlink{classutl_1_1__1wire__i}{\+\_\+1wire\+\_\+i}}
  34. \end{DoxySeeAlso}
  35. Definition at line 52 of file \+\_\+1wire\+\_\+uart.\+h.
  36. \subsection{Member Typedef Documentation}
  37. \mbox{\Hypertarget{classutl_1_1__1wire__uart__i_acc4364e3aa029405a9b2b25e1fea83ac}\label{classutl_1_1__1wire__uart__i_acc4364e3aa029405a9b2b25e1fea83ac}}
  38. \index{utl\+::\+\_\+1wire\+\_\+uart\+\_\+i@{utl\+::\+\_\+1wire\+\_\+uart\+\_\+i}!Speed@{Speed}}
  39. \index{Speed@{Speed}!utl\+::\+\_\+1wire\+\_\+uart\+\_\+i@{utl\+::\+\_\+1wire\+\_\+uart\+\_\+i}}
  40. \subsubsection{\texorpdfstring{Speed}{Speed}}
  41. {\footnotesize\ttfamily template$<$typename Impl\+\_\+t$>$ \\
  42. using \mbox{\hyperlink{classutl_1_1__1wire__uart__i}{utl\+::\+\_\+1wire\+\_\+uart\+\_\+i}}$<$ Impl\+\_\+t $>$\+::\mbox{\hyperlink{classutl_1_1__1wire__uart__i_acc4364e3aa029405a9b2b25e1fea83ac}{Speed}} = typename \mbox{\hyperlink{classutl_1_1__1wire__i}{\+\_\+1wire\+\_\+i}}$<$\mbox{\hyperlink{classutl_1_1__1wire__uart__i_acc885c6ec2395ad20409b01aa4d5f546}{type}}$>$\+::\mbox{\hyperlink{classutl_1_1__1wire__uart__i_acc4364e3aa029405a9b2b25e1fea83ac}{Speed}}}
  43. Bring bus speed.
  44. Definition at line 57 of file \+\_\+1wire\+\_\+uart.\+h.
  45. \mbox{\Hypertarget{classutl_1_1__1wire__uart__i_acc885c6ec2395ad20409b01aa4d5f546}\label{classutl_1_1__1wire__uart__i_acc885c6ec2395ad20409b01aa4d5f546}}
  46. \index{utl\+::\+\_\+1wire\+\_\+uart\+\_\+i@{utl\+::\+\_\+1wire\+\_\+uart\+\_\+i}!type@{type}}
  47. \index{type@{type}!utl\+::\+\_\+1wire\+\_\+uart\+\_\+i@{utl\+::\+\_\+1wire\+\_\+uart\+\_\+i}}
  48. \subsubsection{\texorpdfstring{type}{type}}
  49. {\footnotesize\ttfamily template$<$typename Impl\+\_\+t$>$ \\
  50. using \mbox{\hyperlink{classutl_1_1__1wire__uart__i}{utl\+::\+\_\+1wire\+\_\+uart\+\_\+i}}$<$ Impl\+\_\+t $>$\+::\mbox{\hyperlink{classutl_1_1__1wire__uart__i_acc885c6ec2395ad20409b01aa4d5f546}{type}} = \mbox{\hyperlink{classutl_1_1__1wire__uart__i}{\+\_\+1wire\+\_\+uart\+\_\+i}}$<$Impl\+\_\+t$>$}
  51. Export type as identity meta-\/function.
  52. Definition at line 56 of file \+\_\+1wire\+\_\+uart.\+h.
  53. \subsection{Constructor \& Destructor Documentation}
  54. \mbox{\Hypertarget{classutl_1_1__1wire__uart__i_ae14ed1ce068d5601c5623c410a0dbc0c}\label{classutl_1_1__1wire__uart__i_ae14ed1ce068d5601c5623c410a0dbc0c}}
  55. \index{utl\+::\+\_\+1wire\+\_\+uart\+\_\+i@{utl\+::\+\_\+1wire\+\_\+uart\+\_\+i}!\+\_\+1wire\+\_\+uart\+\_\+i@{\+\_\+1wire\+\_\+uart\+\_\+i}}
  56. \index{\+\_\+1wire\+\_\+uart\+\_\+i@{\+\_\+1wire\+\_\+uart\+\_\+i}!utl\+::\+\_\+1wire\+\_\+uart\+\_\+i@{utl\+::\+\_\+1wire\+\_\+uart\+\_\+i}}
  57. \subsubsection{\texorpdfstring{\+\_\+1wire\+\_\+uart\+\_\+i()}{\_1wire\_uart\_i()}}
  58. {\footnotesize\ttfamily template$<$typename Impl\+\_\+t$>$ \\
  59. \mbox{\hyperlink{classutl_1_1__1wire__uart__i}{utl\+::\+\_\+1wire\+\_\+uart\+\_\+i}}$<$ Impl\+\_\+t $>$\+::\mbox{\hyperlink{classutl_1_1__1wire__uart__i}{\+\_\+1wire\+\_\+uart\+\_\+i}} (\begin{DoxyParamCaption}{ }\end{DoxyParamCaption})\hspace{0.3cm}{\ttfamily [protected]}, {\ttfamily [default]}}
  60. Allow constructor from derived only.
  61. \mbox{\Hypertarget{classutl_1_1__1wire__uart__i_afe64da15b5eaf61cd54f357f3ea8b3ea}\label{classutl_1_1__1wire__uart__i_afe64da15b5eaf61cd54f357f3ea8b3ea}}
  62. \index{utl\+::\+\_\+1wire\+\_\+uart\+\_\+i@{utl\+::\+\_\+1wire\+\_\+uart\+\_\+i}!````~\+\_\+1wire\+\_\+uart\+\_\+i@{$\sim$\+\_\+1wire\+\_\+uart\+\_\+i}}
  63. \index{````~\+\_\+1wire\+\_\+uart\+\_\+i@{$\sim$\+\_\+1wire\+\_\+uart\+\_\+i}!utl\+::\+\_\+1wire\+\_\+uart\+\_\+i@{utl\+::\+\_\+1wire\+\_\+uart\+\_\+i}}
  64. \subsubsection{\texorpdfstring{$\sim$\+\_\+1wire\+\_\+uart\+\_\+i()}{~\_1wire\_uart\_i()}}
  65. {\footnotesize\ttfamily template$<$typename Impl\+\_\+t$>$ \\
  66. \mbox{\hyperlink{classutl_1_1__1wire__uart__i}{utl\+::\+\_\+1wire\+\_\+uart\+\_\+i}}$<$ Impl\+\_\+t $>$\+::$\sim$\mbox{\hyperlink{classutl_1_1__1wire__uart__i}{\+\_\+1wire\+\_\+uart\+\_\+i}} (\begin{DoxyParamCaption}{ }\end{DoxyParamCaption})\hspace{0.3cm}{\ttfamily [protected]}, {\ttfamily [default]}}
  67. Allow destructor from derived only
  68. The documentation for this class was generated from the following file\+:\begin{DoxyCompactItemize}
  69. \item
  70. include/utl/com/\mbox{\hyperlink{__1wire__uart_8h}{\+\_\+1wire\+\_\+uart.\+h}}\end{DoxyCompactItemize}