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A bundled STM32F10x Std Periph and CMSIS library
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STM32F10x_Std_Lib/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rcc.h

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  1. /*

  2.  * stm32f10x_rcc.c

  3.  *

  4.  * Copyright (C) 2013 Houtouridis Christos <houtouridis.ch@gmail.com>

  5.  *

  6.  * All Rights Reserved.

  7.  *

  8.  * NOTICE:  All information contained herein is, and remains

  9.  * the property of Houtouridis Christos. The intellectual

  10.  * and technical concepts contained herein are proprietary to

  11.  * Houtouridis Christos and are protected by copyright law.

  12.  * Dissemination of this information or reproduction of this material

  13.  * is strictly forbidden unless prior written permission is obtained

  14.  * from Houtouridis Christos.

  15.  *

  16.  * Author:     Houtouridis Christos <houtouridis.ch@gmail.com>

  17.  * Date:       4 Áðñ 2013

  18.  *

  19.  */

  20. 

  21. 

  22. #ifndef __STM32F10x_RCC_H__

  23. #define __STM32F10x_RCC_H__

  24. 

  25. #ifdef __cplusplus

  26. extern "C" {

  27. #endif

  28. 

  29. #include "stm32f10x.h"

  30. #include "stm32f10x_assert.h"

  31. 

  32. /* =========================  User Defines ============================*/

  33. #define RCC_USE_IT               (0)

  34. 

  35. 

  36. 

  37. /* HSE_configuration */

  38. #define RCC_HSE_OFF                       ((uint32_t)0x00000000)

  39. #define RCC_HSE_ON                        ((uint32_t)0x00010000)

  40. #define RCC_HSE_Bypass                    ((uint32_t)0x00040000)

  41. #define IS_RCC_HSE(HSE)                   (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \

  42.                                           ((HSE) == RCC_HSE_Bypass))

  43. 

  44. 

  45. // PLL_entry_clock_source

  46. #define RCC_PLLSource_HSI_Div2           ((uint32_t)0x00000000)

  47. 

  48. #if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_CL)

  49.  #define RCC_PLLSource_HSE_Div1           ((uint32_t)0x00010000)

  50.  #define RCC_PLLSource_HSE_Div2           ((uint32_t)0x00030000)

  51.  #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \

  52.                                    ((SOURCE) == RCC_PLLSource_HSE_Div1) || \

  53.                                    ((SOURCE) == RCC_PLLSource_HSE_Div2))

  54. #else

  55.  #define RCC_PLLSource_PREDIV1            ((uint32_t)0x00010000)

  56.  #define IS_RCC_PLL_SOURCE(SOURCE)        (((SOURCE) == RCC_PLLSource_HSI_Div2) || \

  57.                                           ((SOURCE) == RCC_PLLSource_PREDIV1))

  58. #endif /* STM32F10X_CL */

  59. 

  60. // PLL_multiplication_factor

  61. #ifndef STM32F10X_CL

  62.  #define RCC_PLLMul_2            ((uint32_t)0x00000000)

  63.  #define RCC_PLLMul_3            ((uint32_t)0x00040000)

  64.  #define RCC_PLLMul_4            ((uint32_t)0x00080000)

  65.  #define RCC_PLLMul_5            ((uint32_t)0x000C0000)

  66.  #define RCC_PLLMul_6            ((uint32_t)0x00100000)

  67.  #define RCC_PLLMul_7            ((uint32_t)0x00140000)

  68.  #define RCC_PLLMul_8            ((uint32_t)0x00180000)

  69.  #define RCC_PLLMul_9            ((uint32_t)0x001C0000)

  70.  #define RCC_PLLMul_10           ((uint32_t)0x00200000)

  71.  #define RCC_PLLMul_11           ((uint32_t)0x00240000)

  72.  #define RCC_PLLMul_12           ((uint32_t)0x00280000)

  73.  #define RCC_PLLMul_13           ((uint32_t)0x002C0000)

  74.  #define RCC_PLLMul_14           ((uint32_t)0x00300000)

  75.  #define RCC_PLLMul_15           ((uint32_t)0x00340000)

  76.  #define RCC_PLLMul_16           ((uint32_t)0x00380000)

  77.  #define IS_RCC_PLL_MUL(MUL)     (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3)  || \

  78.                                  ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5)   || \

  79.                                  ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7)   || \

  80.                                  ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9)   || \

  81.                                  ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \

  82.                                  ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \

  83.                                  ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \

  84.                                  ((MUL) == RCC_PLLMul_16))

  85. 

  86. #else

  87.  #define RCC_PLLMul_4                    ((uint32_t)0x00080000)

  88.  #define RCC_PLLMul_5                    ((uint32_t)0x000C0000)

  89.  #define RCC_PLLMul_6                    ((uint32_t)0x00100000)

  90.  #define RCC_PLLMul_7                    ((uint32_t)0x00140000)

  91.  #define RCC_PLLMul_8                    ((uint32_t)0x00180000)

  92.  #define RCC_PLLMul_9                    ((uint32_t)0x001C0000)

  93.  #define RCC_PLLMul_6_5                  ((uint32_t)0x00340000)

  94. 

  95.  #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \

  96.                               ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \

  97.                               ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \

  98.                               ((MUL) == RCC_PLLMul_6_5))

  99. #endif /* STM32F10X_CL */

  100. 

  101. 

  102. //PREDIV1_division_factor

  103. #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL)

  104.  #define  RCC_PREDIV1_Div1               ((uint32_t)0x00000000)

  105.  #define  RCC_PREDIV1_Div2               ((uint32_t)0x00000001)

  106.  #define  RCC_PREDIV1_Div3               ((uint32_t)0x00000002)

  107.  #define  RCC_PREDIV1_Div4               ((uint32_t)0x00000003)

  108.  #define  RCC_PREDIV1_Div5               ((uint32_t)0x00000004)

  109.  #define  RCC_PREDIV1_Div6               ((uint32_t)0x00000005)

  110.  #define  RCC_PREDIV1_Div7               ((uint32_t)0x00000006)

  111.  #define  RCC_PREDIV1_Div8               ((uint32_t)0x00000007)

  112.  #define  RCC_PREDIV1_Div9               ((uint32_t)0x00000008)

  113.  #define  RCC_PREDIV1_Div10              ((uint32_t)0x00000009)

  114.  #define  RCC_PREDIV1_Div11              ((uint32_t)0x0000000A)

  115.  #define  RCC_PREDIV1_Div12              ((uint32_t)0x0000000B)

  116.  #define  RCC_PREDIV1_Div13              ((uint32_t)0x0000000C)

  117.  #define  RCC_PREDIV1_Div14              ((uint32_t)0x0000000D)

  118.  #define  RCC_PREDIV1_Div15              ((uint32_t)0x0000000E)

  119.  #define  RCC_PREDIV1_Div16              ((uint32_t)0x0000000F)

  120. 

  121.  #define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \

  122.                                   ((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \

  123.                                   ((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \

  124.                                   ((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \

  125.                                   ((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \

  126.                                   ((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \

  127.                                   ((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \

  128.                                   ((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16))

  129. #endif

  130. 

  131. 

  132. // PREDIV1_clock_source

  133. #ifdef STM32F10X_CL

  134. /* PREDIV1 clock source (for STM32 connectivity line devices) */

  135.  #define  RCC_PREDIV1_Source_HSE         ((uint32_t)0x00000000)

  136.  #define  RCC_PREDIV1_Source_PLL2        ((uint32_t)0x00010000)

  137. 

  138.  #define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE) || \

  139.                                         ((SOURCE) == RCC_PREDIV1_Source_PLL2))

  140. #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)

  141. /* PREDIV1 clock source (for STM32 Value line devices) */

  142.  #define  RCC_PREDIV1_Source_HSE         ((uint32_t)0x00000000)

  143. 

  144.  #define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE))

  145. #endif

  146. /**

  147.   * @}

  148.   */

  149. 

  150. #ifdef STM32F10X_CL

  151. 

  152. // PREDIV2_division_factor

  153.  #define  RCC_PREDIV2_Div1               ((uint32_t)0x00000000)

  154.  #define  RCC_PREDIV2_Div2               ((uint32_t)0x00000010)

  155.  #define  RCC_PREDIV2_Div3               ((uint32_t)0x00000020)

  156.  #define  RCC_PREDIV2_Div4               ((uint32_t)0x00000030)

  157.  #define  RCC_PREDIV2_Div5               ((uint32_t)0x00000040)

  158.  #define  RCC_PREDIV2_Div6               ((uint32_t)0x00000050)

  159.  #define  RCC_PREDIV2_Div7               ((uint32_t)0x00000060)

  160.  #define  RCC_PREDIV2_Div8               ((uint32_t)0x00000070)

  161.  #define  RCC_PREDIV2_Div9               ((uint32_t)0x00000080)

  162.  #define  RCC_PREDIV2_Div10              ((uint32_t)0x00000090)

  163.  #define  RCC_PREDIV2_Div11              ((uint32_t)0x000000A0)

  164.  #define  RCC_PREDIV2_Div12              ((uint32_t)0x000000B0)

  165.  #define  RCC_PREDIV2_Div13              ((uint32_t)0x000000C0)

  166.  #define  RCC_PREDIV2_Div14              ((uint32_t)0x000000D0)

  167.  #define  RCC_PREDIV2_Div15              ((uint32_t)0x000000E0)

  168.  #define  RCC_PREDIV2_Div16              ((uint32_t)0x000000F0)

  169. 

  170.  #define IS_RCC_PREDIV2(PREDIV2) (((PREDIV2) == RCC_PREDIV2_Div1) || ((PREDIV2) == RCC_PREDIV2_Div2) || \

  171.                                   ((PREDIV2) == RCC_PREDIV2_Div3) || ((PREDIV2) == RCC_PREDIV2_Div4) || \

  172.                                   ((PREDIV2) == RCC_PREDIV2_Div5) || ((PREDIV2) == RCC_PREDIV2_Div6) || \

  173.                                   ((PREDIV2) == RCC_PREDIV2_Div7) || ((PREDIV2) == RCC_PREDIV2_Div8) || \

  174.                                   ((PREDIV2) == RCC_PREDIV2_Div9) || ((PREDIV2) == RCC_PREDIV2_Div10) || \

  175.                                   ((PREDIV2) == RCC_PREDIV2_Div11) || ((PREDIV2) == RCC_PREDIV2_Div12) || \

  176.                                   ((PREDIV2) == RCC_PREDIV2_Div13) || ((PREDIV2) == RCC_PREDIV2_Div14) || \

  177.                                   ((PREDIV2) == RCC_PREDIV2_Div15) || ((PREDIV2) == RCC_PREDIV2_Div16))

  178. 

  179. // PLL2_multiplication_factor

  180.  #define  RCC_PLL2Mul_8                  ((uint32_t)0x00000600)

  181.  #define  RCC_PLL2Mul_9                  ((uint32_t)0x00000700)

  182.  #define  RCC_PLL2Mul_10                 ((uint32_t)0x00000800)

  183.  #define  RCC_PLL2Mul_11                 ((uint32_t)0x00000900)

  184.  #define  RCC_PLL2Mul_12                 ((uint32_t)0x00000A00)

  185.  #define  RCC_PLL2Mul_13                 ((uint32_t)0x00000B00)

  186.  #define  RCC_PLL2Mul_14                 ((uint32_t)0x00000C00)

  187.  #define  RCC_PLL2Mul_16                 ((uint32_t)0x00000E00)

  188.  #define  RCC_PLL2Mul_20                 ((uint32_t)0x00000F00)

  189. 

  190.  #define IS_RCC_PLL2_MUL(MUL) (((MUL) == RCC_PLL2Mul_8) || ((MUL) == RCC_PLL2Mul_9)  || \

  191.                                ((MUL) == RCC_PLL2Mul_10) || ((MUL) == RCC_PLL2Mul_11) || \

  192.                                ((MUL) == RCC_PLL2Mul_12) || ((MUL) == RCC_PLL2Mul_13) || \

  193.                                ((MUL) == RCC_PLL2Mul_14) || ((MUL) == RCC_PLL2Mul_16) || \

  194.                                ((MUL) == RCC_PLL2Mul_20))

  195. 

  196. // PLL3_multiplication_factor

  197.  #define  RCC_PLL3Mul_8                  ((uint32_t)0x00006000)

  198.  #define  RCC_PLL3Mul_9                  ((uint32_t)0x00007000)

  199.  #define  RCC_PLL3Mul_10                 ((uint32_t)0x00008000)

  200.  #define  RCC_PLL3Mul_11                 ((uint32_t)0x00009000)

  201.  #define  RCC_PLL3Mul_12                 ((uint32_t)0x0000A000)

  202.  #define  RCC_PLL3Mul_13                 ((uint32_t)0x0000B000)

  203.  #define  RCC_PLL3Mul_14                 ((uint32_t)0x0000C000)

  204.  #define  RCC_PLL3Mul_16                 ((uint32_t)0x0000E000)

  205.  #define  RCC_PLL3Mul_20                 ((uint32_t)0x0000F000)

  206. 

  207.  #define IS_RCC_PLL3_MUL(MUL) (((MUL) == RCC_PLL3Mul_8) || ((MUL) == RCC_PLL3Mul_9)  || \

  208.                                ((MUL) == RCC_PLL3Mul_10) || ((MUL) == RCC_PLL3Mul_11) || \

  209.                                ((MUL) == RCC_PLL3Mul_12) || ((MUL) == RCC_PLL3Mul_13) || \

  210.                                ((MUL) == RCC_PLL3Mul_14) || ((MUL) == RCC_PLL3Mul_16) || \

  211.                                ((MUL) == RCC_PLL3Mul_20))

  212. 

  213. #endif /* STM32F10X_CL */

  214. 

  215. 

  216. // System_clock_source

  217. #define RCC_SYSCLKSource_HSI             ((uint32_t)0x00000000)

  218. #define RCC_SYSCLKSource_HSE             ((uint32_t)0x00000001)

  219. #define RCC_SYSCLKSource_PLLCLK          ((uint32_t)0x00000002)

  220. #define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \

  221.                                       ((SOURCE) == RCC_SYSCLKSource_HSE) || \

  222.                                       ((SOURCE) == RCC_SYSCLKSource_PLLCLK))

  223. 

  224. // AHB_clock_source

  225. #define RCC_SYSCLK_Div1                  ((uint32_t)0x00000000)

  226. #define RCC_SYSCLK_Div2                  ((uint32_t)0x00000080)

  227. #define RCC_SYSCLK_Div4                  ((uint32_t)0x00000090)

  228. #define RCC_SYSCLK_Div8                  ((uint32_t)0x000000A0)

  229. #define RCC_SYSCLK_Div16                 ((uint32_t)0x000000B0)

  230. #define RCC_SYSCLK_Div64                 ((uint32_t)0x000000C0)

  231. #define RCC_SYSCLK_Div128                ((uint32_t)0x000000D0)

  232. #define RCC_SYSCLK_Div256                ((uint32_t)0x000000E0)

  233. #define RCC_SYSCLK_Div512                ((uint32_t)0x000000F0)

  234. #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \

  235.                            ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \

  236.                            ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \

  237.                            ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \

  238.                            ((HCLK) == RCC_SYSCLK_Div512))

  239. 

  240. // APB1_APB2_clock_source

  241. #define RCC_HCLK_Div1                    ((uint32_t)0x00000000)

  242. #define RCC_HCLK_Div2                    ((uint32_t)0x00000400)

  243. #define RCC_HCLK_Div4                    ((uint32_t)0x00000500)

  244. #define RCC_HCLK_Div8                    ((uint32_t)0x00000600)

  245. #define RCC_HCLK_Div16                   ((uint32_t)0x00000700)

  246. #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \

  247.                            ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \

  248.                            ((PCLK) == RCC_HCLK_Div16))

  249. 

  250. // RCC_Interrupt_source

  251. #define RCC_IT_LSIRDY                    ((uint8_t)0x01)

  252. #define RCC_IT_LSERDY                    ((uint8_t)0x02)

  253. #define RCC_IT_HSIRDY                    ((uint8_t)0x04)

  254. #define RCC_IT_HSERDY                    ((uint8_t)0x08)

  255. #define RCC_IT_PLLRDY                    ((uint8_t)0x10)

  256. #define RCC_IT_CSS                       ((uint8_t)0x80)

  257. 

  258. #ifndef STM32F10X_CL

  259.  #define IS_RCC_IT(IT)           ((((IT) & (uint8_t)0xE0) == 0x00) && ((IT) != 0x00))

  260.  #define IS_RCC_GET_IT(IT)       (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \

  261.                                  ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \

  262.                                  ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS))

  263.  #define IS_RCC_CLEAR_IT(IT)     ((((IT) & (uint8_t)0x60) == 0x00) && ((IT) != 0x00))

  264. #else

  265.  #define RCC_IT_PLL2RDY                  ((uint8_t)0x20)

  266.  #define RCC_IT_PLL3RDY                  ((uint8_t)0x40)

  267.  #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00))

  268.  #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \

  269.                             ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \

  270.                             ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \

  271.                             ((IT) == RCC_IT_PLL2RDY) || ((IT) == RCC_IT_PLL3RDY))

  272.  #define IS_RCC_CLEAR_IT(IT) ((IT) != 0x00)

  273. #endif /* STM32F10X_CL */

  274. 

  275. 

  276. #ifndef STM32F10X_CL

  277. 

  278. // USB_Device_clock_source

  279.  #define RCC_USBCLKSource_PLLCLK_1Div5    ((uint8_t)0x00)

  280.  #define RCC_USBCLKSource_PLLCLK_Div1     ((uint8_t)0x01)

  281. 

  282.  #define IS_RCC_USBCLK_SOURCE(SOURCE)     (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \

  283.                                           ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1))

  284. 

  285. #else

  286. 

  287. // USB_OTG_FS_clock_source

  288.  #define RCC_OTGFSCLKSource_PLLVCO_Div3   ((uint8_t)0x00)

  289.  #define RCC_OTGFSCLKSource_PLLVCO_Div2   ((uint8_t)0x01)

  290. 

  291.  #define IS_RCC_OTGFSCLK_SOURCE(SOURCE)   (((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div3) || \

  292.                                           ((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div2))

  293. 

  294. #endif /* STM32F10X_CL */

  295. 

  296. 

  297. #ifdef STM32F10X_CL

  298. 

  299. // I2S2_clock_source

  300.  #define RCC_I2S2CLKSource_SYSCLK         ((uint8_t)0x00)

  301.  #define RCC_I2S2CLKSource_PLL3_VCO       ((uint8_t)0x01)

  302. 

  303.  #define IS_RCC_I2S2CLK_SOURCE(SOURCE)    (((SOURCE) == RCC_I2S2CLKSource_SYSCLK) || \

  304.                                           ((SOURCE) == RCC_I2S2CLKSource_PLL3_VCO))

  305. 

  306. 

  307. // I2S3_clock_source

  308.  #define RCC_I2S3CLKSource_SYSCLK         ((uint8_t)0x00)

  309.  #define RCC_I2S3CLKSource_PLL3_VCO       ((uint8_t)0x01)

  310. 

  311.  #define IS_RCC_I2S3CLK_SOURCE(SOURCE)    (((SOURCE) == RCC_I2S3CLKSource_SYSCLK) || \

  312.                                           ((SOURCE) == RCC_I2S3CLKSource_PLL3_VCO))

  313. 

  314. #endif /* STM32F10X_CL */

  315. 

  316. 

  317. // ADC_clock_source

  318. #define RCC_PCLK2_Div2              ((uint32_t)0x00000000)

  319. #define RCC_PCLK2_Div4              ((uint32_t)0x00004000)

  320. #define RCC_PCLK2_Div6              ((uint32_t)0x00008000)

  321. #define RCC_PCLK2_Div8              ((uint32_t)0x0000C000)

  322. #define IS_RCC_ADCCLK(ADCCLK)       (((ADCCLK) == RCC_PCLK2_Div2) || ((ADCCLK) == RCC_PCLK2_Div4) || \

  323.                                     ((ADCCLK) == RCC_PCLK2_Div6) || ((ADCCLK) == RCC_PCLK2_Div8))

  324. 

  325. // LSE_configuration

  326. #define RCC_LSE_OFF                 ((uint8_t)0x00)

  327. #define RCC_LSE_ON                  ((uint8_t)0x01)

  328. #define RCC_LSE_Bypass              ((uint8_t)0x04)

  329. #define IS_RCC_LSE(LSE)             (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \

  330.                                     ((LSE) == RCC_LSE_Bypass))

  331. 

  332. // RTC_clock_source

  333. #define RCC_RTCCLKSource_LSE           ((uint32_t)0x00000100)

  334. #define RCC_RTCCLKSource_LSI           ((uint32_t)0x00000200)

  335. #define RCC_RTCCLKSource_HSE_Div128    ((uint32_t)0x00000300)

  336. #define IS_RCC_RTCCLK_SOURCE(SOURCE)   (((SOURCE) == RCC_RTCCLKSource_LSE) || \

  337.                                        ((SOURCE) == RCC_RTCCLKSource_LSI) || \

  338.                                        ((SOURCE) == RCC_RTCCLKSource_HSE_Div128))

  339. 

  340. // AHB_peripheral

  341. #define RCC_AHBPeriph_DMA1             ((uint32_t)0x00000001)

  342. #define RCC_AHBPeriph_DMA2             ((uint32_t)0x00000002)

  343. #define RCC_AHBPeriph_SRAM             ((uint32_t)0x00000004)

  344. #define RCC_AHBPeriph_FLITF            ((uint32_t)0x00000010)

  345. #define RCC_AHBPeriph_CRC              ((uint32_t)0x00000040)

  346. 

  347. #ifndef STM32F10X_CL

  348.  #define RCC_AHBPeriph_FSMC            ((uint32_t)0x00000100)

  349.  #define RCC_AHBPeriph_SDIO            ((uint32_t)0x00000400)

  350.  #define IS_RCC_AHB_PERIPH(PERIPH)     ((((PERIPH) & 0xFFFFFAA8) == 0x00) && ((PERIPH) != 0x00))

  351. #else

  352.  #define RCC_AHBPeriph_OTG_FS            ((uint32_t)0x00001000)

  353.  #define RCC_AHBPeriph_ETH_MAC           ((uint32_t)0x00004000)

  354.  #define RCC_AHBPeriph_ETH_MAC_Tx        ((uint32_t)0x00008000)

  355.  #define RCC_AHBPeriph_ETH_MAC_Rx        ((uint32_t)0x00010000)

  356. 

  357.  #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFE2FA8) == 0x00) && ((PERIPH) != 0x00))

  358.  #define IS_RCC_AHB_PERIPH_RESET(PERIPH) ((((PERIPH) & 0xFFFFAFFF) == 0x00) && ((PERIPH) != 0x00))

  359. #endif /* STM32F10X_CL */

  360. 

  361. 

  362. 

  363. // APB2_peripheral

  364. #define RCC_APB2Periph_AFIO              ((uint32_t)0x00000001)

  365. #define RCC_APB2Periph_GPIOA             ((uint32_t)0x00000004)

  366. #define RCC_APB2Periph_GPIOB             ((uint32_t)0x00000008)

  367. #define RCC_APB2Periph_GPIOC             ((uint32_t)0x00000010)

  368. #define RCC_APB2Periph_GPIOD             ((uint32_t)0x00000020)

  369. #define RCC_APB2Periph_GPIOE             ((uint32_t)0x00000040)

  370. #define RCC_APB2Periph_GPIOF             ((uint32_t)0x00000080)

  371. #define RCC_APB2Periph_GPIOG             ((uint32_t)0x00000100)

  372. #define RCC_APB2Periph_ADC1              ((uint32_t)0x00000200)

  373. #define RCC_APB2Periph_ADC2              ((uint32_t)0x00000400)

  374. #define RCC_APB2Periph_TIM1              ((uint32_t)0x00000800)

  375. #define RCC_APB2Periph_SPI1              ((uint32_t)0x00001000)

  376. #define RCC_APB2Periph_TIM8              ((uint32_t)0x00002000)

  377. #define RCC_APB2Periph_USART1            ((uint32_t)0x00004000)

  378. #define RCC_APB2Periph_ADC3              ((uint32_t)0x00008000)

  379. #define RCC_APB2Periph_TIM15             ((uint32_t)0x00010000)

  380. #define RCC_APB2Periph_TIM16             ((uint32_t)0x00020000)

  381. #define RCC_APB2Periph_TIM17             ((uint32_t)0x00040000)

  382. #define RCC_APB2Periph_TIM9              ((uint32_t)0x00080000)

  383. #define RCC_APB2Periph_TIM10             ((uint32_t)0x00100000)

  384. #define RCC_APB2Periph_TIM11             ((uint32_t)0x00200000)

  385. 

  386. #define IS_RCC_APB2_PERIPH(PERIPH)  ((((PERIPH) & 0xFFC00002) == 0x00) && ((PERIPH) != 0x00))

  387. 

  388. 

  389. // APB1_peripheral

  390. #define RCC_APB1Periph_TIM2              ((uint32_t)0x00000001)

  391. #define RCC_APB1Periph_TIM3              ((uint32_t)0x00000002)

  392. #define RCC_APB1Periph_TIM4              ((uint32_t)0x00000004)

  393. #define RCC_APB1Periph_TIM5              ((uint32_t)0x00000008)

  394. #define RCC_APB1Periph_TIM6              ((uint32_t)0x00000010)

  395. #define RCC_APB1Periph_TIM7              ((uint32_t)0x00000020)

  396. #define RCC_APB1Periph_TIM12             ((uint32_t)0x00000040)

  397. #define RCC_APB1Periph_TIM13             ((uint32_t)0x00000080)

  398. #define RCC_APB1Periph_TIM14             ((uint32_t)0x00000100)

  399. #define RCC_APB1Periph_WWDG              ((uint32_t)0x00000800)

  400. #define RCC_APB1Periph_SPI2              ((uint32_t)0x00004000)

  401. #define RCC_APB1Periph_SPI3              ((uint32_t)0x00008000)

  402. #define RCC_APB1Periph_USART2            ((uint32_t)0x00020000)

  403. #define RCC_APB1Periph_USART3            ((uint32_t)0x00040000)

  404. #define RCC_APB1Periph_UART4             ((uint32_t)0x00080000)

  405. #define RCC_APB1Periph_UART5             ((uint32_t)0x00100000)

  406. #define RCC_APB1Periph_I2C1              ((uint32_t)0x00200000)

  407. #define RCC_APB1Periph_I2C2              ((uint32_t)0x00400000)

  408. #define RCC_APB1Periph_USB               ((uint32_t)0x00800000)

  409. #define RCC_APB1Periph_CAN1              ((uint32_t)0x02000000)

  410. #define RCC_APB1Periph_CAN2              ((uint32_t)0x04000000)

  411. #define RCC_APB1Periph_BKP               ((uint32_t)0x08000000)

  412. #define RCC_APB1Periph_PWR               ((uint32_t)0x10000000)

  413. #define RCC_APB1Periph_DAC               ((uint32_t)0x20000000)

  414. #define RCC_APB1Periph_CEC               ((uint32_t)0x40000000)

  415. 

  416. #define IS_RCC_APB1_PERIPH(PERIPH)  ((((PERIPH) & 0x81013600) == 0x00) && ((PERIPH) != 0x00))

  417. 

  418. 

  419. // Clock_source_to_output_on_MCO_pin

  420. #define RCC_MCO_NoClock                  ((uint8_t)0x00)

  421. #define RCC_MCO_SYSCLK                   ((uint8_t)0x04)

  422. #define RCC_MCO_HSI                      ((uint8_t)0x05)

  423. #define RCC_MCO_HSE                      ((uint8_t)0x06)

  424. #define RCC_MCO_PLLCLK_Div2              ((uint8_t)0x07)

  425. 

  426. #ifndef STM32F10X_CL

  427.  #define IS_RCC_MCO(MCO)      (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \

  428.                               ((MCO) == RCC_MCO_SYSCLK)  || ((MCO) == RCC_MCO_HSE) || \

  429.                               ((MCO) == RCC_MCO_PLLCLK_Div2))

  430. #else

  431.  #define RCC_MCO_PLL2CLK                 ((uint8_t)0x08)

  432.  #define RCC_MCO_PLL3CLK_Div2            ((uint8_t)0x09)

  433.  #define RCC_MCO_XT1                     ((uint8_t)0x0A)

  434.  #define RCC_MCO_PLL3CLK                 ((uint8_t)0x0B)

  435. 

  436.  #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \

  437.                           ((MCO) == RCC_MCO_SYSCLK)  || ((MCO) == RCC_MCO_HSE) || \

  438.                           ((MCO) == RCC_MCO_PLLCLK_Div2) || ((MCO) == RCC_MCO_PLL2CLK) || \

  439.                           ((MCO) == RCC_MCO_PLL3CLK_Div2) || ((MCO) == RCC_MCO_XT1) || \

  440.                           ((MCO) == RCC_MCO_PLL3CLK))

  441. #endif /* STM32F10X_CL */

  442. 

  443. 

  444. 

  445. // RCC_Flag

  446. #define RCC_FLAG_HSIRDY                  ((uint8_t)0x21)

  447. #define RCC_FLAG_HSERDY                  ((uint8_t)0x31)

  448. #define RCC_FLAG_PLLRDY                  ((uint8_t)0x39)

  449. #define RCC_FLAG_LSERDY                  ((uint8_t)0x41)

  450. #define RCC_FLAG_LSIRDY                  ((uint8_t)0x61)

  451. #define RCC_FLAG_PINRST                  ((uint8_t)0x7A)

  452. #define RCC_FLAG_PORRST                  ((uint8_t)0x7B)

  453. #define RCC_FLAG_SFTRST                  ((uint8_t)0x7C)

  454. #define RCC_FLAG_IWDGRST                 ((uint8_t)0x7D)

  455. #define RCC_FLAG_WWDGRST                 ((uint8_t)0x7E)

  456. #define RCC_FLAG_LPWRRST                 ((uint8_t)0x7F)

  457. 

  458. #ifndef STM32F10X_CL

  459.  #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \

  460.                             ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \

  461.                             ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \

  462.                             ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \

  463.                             ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \

  464.                             ((FLAG) == RCC_FLAG_LPWRRST))

  465. #else

  466.  #define RCC_FLAG_PLL2RDY                ((uint8_t)0x3B)

  467.  #define RCC_FLAG_PLL3RDY                ((uint8_t)0x3D)

  468.  #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \

  469.                             ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \

  470.                             ((FLAG) == RCC_FLAG_PLL2RDY) || ((FLAG) == RCC_FLAG_PLL3RDY) || \

  471.                             ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \

  472.                             ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \

  473.                             ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \

  474.                             ((FLAG) == RCC_FLAG_LPWRRST))

  475. #endif /* STM32F10X_CL */

  476. 

  477. #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)

  478. 

  479. 

  480. /* ======================== Data types ========================= */

  481. 

  482. /* RCC_Exported_Types*/

  483. typedef struct

  484. {

  485.    uint32_t SYSCLK_Frequency;  /*!< returns SYSCLK clock frequency expressed in Hz */

  486.    uint32_t HCLK_Frequency;    /*!< returns HCLK clock frequency expressed in Hz */

  487.    uint32_t PCLK1_Frequency;   /*!< returns PCLK1 clock frequency expressed in Hz */

  488.    uint32_t PCLK2_Frequency;   /*!< returns PCLK2 clock frequency expressed in Hz */

  489.    uint32_t ADCCLK_Frequency;  /*!< returns ADCCLK clock frequency expressed in Hz */

  490. }RCC_ClocksTypeDef;

  491. 

  492. /* ======================== Exported API ========================= */

  493. 

  494. void RCC_DeInit(void);

  495. void RCC_HSEConfig(uint32_t RCC_HSE);

  496. ErrorStatus RCC_WaitForHSEStartUp(void);

  497. void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);

  498. void RCC_HSICmd(FunctionalState NewState);

  499. void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);

  500. void RCC_PLLCmd(FunctionalState NewState);

  501. 

  502. #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL)

  503.  void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div);

  504. #endif

  505. 

  506. #ifdef  STM32F10X_CL

  507.  void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div);

  508.  void RCC_PLL2Config(uint32_t RCC_PLL2Mul);

  509.  void RCC_PLL2Cmd(FunctionalState NewState);

  510.  void RCC_PLL3Config(uint32_t RCC_PLL3Mul);

  511.  void RCC_PLL3Cmd(FunctionalState NewState);

  512. #endif /* STM32F10X_CL */

  513. 

  514. void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);

  515. uint8_t RCC_GetSYSCLKSource(void);

  516. void RCC_HCLKConfig(uint32_t RCC_SYSCLK);

  517. void RCC_PCLK1Config(uint32_t RCC_HCLK);

  518. void RCC_PCLK2Config(uint32_t RCC_HCLK);

  519. void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);

  520. 

  521. #ifndef STM32F10X_CL

  522.  void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource);

  523. #else

  524.  void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource);

  525. #endif /* STM32F10X_CL */

  526. 

  527. void RCC_ADCCLKConfig(uint32_t RCC_PCLK2);

  528. 

  529. #ifdef STM32F10X_CL

  530.  void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource);

  531.  void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource);

  532. #endif /* STM32F10X_CL */

  533. 

  534. void RCC_LSEConfig(uint8_t RCC_LSE);

  535. void RCC_LSICmd(FunctionalState NewState);

  536. void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);

  537. void RCC_RTCCLKCmd(FunctionalState NewState);

  538. void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);

  539. void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);

  540. void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);

  541. void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);

  542. 

  543. #ifdef STM32F10X_CL

  544. void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);

  545. #endif /* STM32F10X_CL */

  546. 

  547. void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);

  548. void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);

  549. void RCC_BackupResetCmd(FunctionalState NewState);

  550. void RCC_ClockSecuritySystemCmd(FunctionalState NewState);

  551. void RCC_MCOConfig(uint8_t RCC_MCO);

  552. FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);

  553. void RCC_ClearFlag(void);

  554. #if RCC_USE_IT == 1

  555. ITStatus RCC_GetITStatus(uint8_t RCC_IT);

  556. void RCC_ClearITPendingBit(uint8_t RCC_IT);

  557. #endif

  558. #ifdef __cplusplus

  559. }

  560. #endif

  561. 

  562. #endif /* __STM32F10x_RCC_H__ */

  563. 

  564. 

  565. /*****END OF FILE****/