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A bundled STM32F10x Std Periph and CMSIS library
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STM32F10x_Std_Lib/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init...

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  1. /* ----------------------------------------------------------------------    

  2. * Copyright (C) 2010-2014 ARM Limited. All rights reserved.    

  3. *    

  4. * $Date:        12. March 2014

  5. * $Revision: 	V1.4.4

  6. *    

  7. * Project: 	    CMSIS DSP Library    

  8. * Title:	    arm_biquad_cascade_df1_init_q31.c    

  9. *    

  10. * Description:	Q31 Biquad cascade DirectFormI(DF1) filter initialization function.    

  11. *    

  12. *    

  13. * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0

  14. *  

  15. * Redistribution and use in source and binary forms, with or without 

  16. * modification, are permitted provided that the following conditions

  17. * are met:

  18. *   - Redistributions of source code must retain the above copyright

  19. *     notice, this list of conditions and the following disclaimer.

  20. *   - Redistributions in binary form must reproduce the above copyright

  21. *     notice, this list of conditions and the following disclaimer in

  22. *     the documentation and/or other materials provided with the 

  23. *     distribution.

  24. *   - Neither the name of ARM LIMITED nor the names of its contributors

  25. *     may be used to endorse or promote products derived from this

  26. *     software without specific prior written permission.

  27. *

  28. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS

  29. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT

  30. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS

  31. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 

  32. * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,

  33. * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,

  34. * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;

  35. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER

  36. * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT

  37. * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN

  38. * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE

  39. * POSSIBILITY OF SUCH DAMAGE.    

  40. * -------------------------------------------------------------------- */

  41. 

  42. #include "arm_math.h"

  43. 

  44. /**    

  45.  * @ingroup groupFilters    

  46.  */

  47. 

  48. /**    

  49.  * @addtogroup BiquadCascadeDF1    

  50.  * @{    

  51.  */

  52. 

  53. /**    

  54.  * @details    

  55.  *    

  56.  * @param[in,out] *S           points to an instance of the Q31 Biquad cascade structure.    

  57.  * @param[in]     numStages    number of 2nd order stages in the filter.    

  58.  * @param[in]     *pCoeffs     points to the filter coefficients buffer.    

  59.  * @param[in]     *pState      points to the state buffer.    

  60.  * @param[in]     postShift    Shift to be applied after the accumulator.  Varies according to the coefficients format    

  61.  * @return        none    

  62.  *    

  63.  * <b>Coefficient and State Ordering:</b>    

  64.  *    

  65.  * \par    

  66.  * The coefficients are stored in the array <code>pCoeffs</code> in the following order:    

  67.  * <pre>    

  68.  *     {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}    

  69.  * </pre>    

  70.  * where <code>b1x</code> and <code>a1x</code> are the coefficients for the first stage,    

  71.  * <code>b2x</code> and <code>a2x</code> are the coefficients for the second stage,    

  72.  * and so on.  The <code>pCoeffs</code> array contains a total of <code>5*numStages</code> values.    

  73.  *    

  74.  * \par    

  75.  * The <code>pState</code> points to state variables array.    

  76.  * Each Biquad stage has 4 state variables <code>x[n-1], x[n-2], y[n-1],</code> and <code>y[n-2]</code>.    

  77.  * The state variables are arranged in the <code>pState</code> array as:    

  78.  * <pre>    

  79.  *     {x[n-1], x[n-2], y[n-1], y[n-2]}    

  80.  * </pre>    

  81.  * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.    

  82.  * The state array has a total length of <code>4*numStages</code> values.    

  83.  * The state variables are updated after each block of data is processed; the coefficients are untouched.    

  84.  */

  85. 

  86. void arm_biquad_cascade_df1_init_q31(

  87.   arm_biquad_casd_df1_inst_q31 * S,

  88.   uint8_t numStages,

  89.   q31_t * pCoeffs,

  90.   q31_t * pState,

  91.   int8_t postShift)

  92. {

  93.   /* Assign filter stages */

  94.   S->numStages = numStages;

  95. 

  96.   /* Assign postShift to be applied to the output */

  97.   S->postShift = postShift;

  98. 

  99.   /* Assign coefficient pointer */

  100.   S->pCoeffs = pCoeffs;

  101. 

  102.   /* Clear state buffer and size is always 4 * numStages */

  103.   memset(pState, 0, (4u * (uint32_t) numStages) * sizeof(q31_t));

  104. 

  105.   /* Assign state pointer */

  106.   S->pState = pState;

  107. }

  108. 

  109. /**    

  110.  * @} end of BiquadCascadeDF1 group    

  111.  */