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A bundled STM32F10x Std Periph and CMSIS library
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STM32F10x_Std_Lib/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init...

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  1. /*-----------------------------------------------------------------------------    

  2. * Copyright (C) 2010-2014 ARM Limited. All rights reserved.    

  3. *    

  4. * $Date:        12. March 2014

  5. * $Revision: 	V1.4.4

  6. *    

  7. * Project: 	    CMSIS DSP Library    

  8. * Title:        arm_biquad_cascade_df1_init_f32.c    

  9. *    

  10. * Description:  floating-point Biquad cascade DirectFormI(DF1) filter initialization function.    

  11. *    

  12. * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0

  13. *  

  14. * Redistribution and use in source and binary forms, with or without 

  15. * modification, are permitted provided that the following conditions

  16. * are met:

  17. *   - Redistributions of source code must retain the above copyright

  18. *     notice, this list of conditions and the following disclaimer.

  19. *   - Redistributions in binary form must reproduce the above copyright

  20. *     notice, this list of conditions and the following disclaimer in

  21. *     the documentation and/or other materials provided with the 

  22. *     distribution.

  23. *   - Neither the name of ARM LIMITED nor the names of its contributors

  24. *     may be used to endorse or promote products derived from this

  25. *     software without specific prior written permission.

  26. *

  27. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS

  28. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT

  29. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS

  30. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 

  31. * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,

  32. * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,

  33. * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;

  34. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER

  35. * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT

  36. * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN

  37. * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE

  38. * POSSIBILITY OF SUCH DAMAGE.    

  39. * ---------------------------------------------------------------------------*/

  40. 

  41. #include "arm_math.h"

  42. 

  43. /**    

  44.  * @ingroup groupFilters    

  45.  */

  46. 

  47. /**    

  48.  * @addtogroup BiquadCascadeDF1    

  49.  * @{    

  50.  */

  51. 

  52. /**    

  53.  * @details    

  54.  * @brief  Initialization function for the floating-point Biquad cascade filter.    

  55.  * @param[in,out] *S           points to an instance of the floating-point Biquad cascade structure.    

  56.  * @param[in]     numStages    number of 2nd order stages in the filter.    

  57.  * @param[in]     *pCoeffs     points to the filter coefficients array.    

  58.  * @param[in]     *pState      points to the state array.    

  59.  * @return        none    

  60.  *    

  61.  *    

  62.  * <b>Coefficient and State Ordering:</b>    

  63.  *    

  64.  * \par    

  65.  * The coefficients are stored in the array <code>pCoeffs</code> in the following order:    

  66.  * <pre>    

  67.  *     {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}    

  68.  * </pre>    

  69.  *    

  70.  * \par    

  71.  * where <code>b1x</code> and <code>a1x</code> are the coefficients for the first stage,    

  72.  * <code>b2x</code> and <code>a2x</code> are the coefficients for the second stage,    

  73.  * and so on.  The <code>pCoeffs</code> array contains a total of <code>5*numStages</code> values.    

  74.  *    

  75.  * \par    

  76.  * The <code>pState</code> is a pointer to state array.    

  77.  * Each Biquad stage has 4 state variables <code>x[n-1], x[n-2], y[n-1],</code> and <code>y[n-2]</code>.    

  78.  * The state variables are arranged in the <code>pState</code> array as:    

  79.  * <pre>    

  80.  *     {x[n-1], x[n-2], y[n-1], y[n-2]}    

  81.  * </pre>    

  82.  * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.    

  83.  * The state array has a total length of <code>4*numStages</code> values.    

  84.  * The state variables are updated after each block of data is processed; the coefficients are untouched.    

  85.  *    

  86.  */

  87. 

  88. void arm_biquad_cascade_df1_init_f32(

  89.   arm_biquad_casd_df1_inst_f32 * S,

  90.   uint8_t numStages,

  91.   float32_t * pCoeffs,

  92.   float32_t * pState)

  93. {

  94.   /* Assign filter stages */

  95.   S->numStages = numStages;

  96. 

  97.   /* Assign coefficient pointer */

  98.   S->pCoeffs = pCoeffs;

  99. 

  100.   /* Clear state buffer and size is always 4 * numStages */

  101.   memset(pState, 0, (4u * (uint32_t) numStages) * sizeof(float32_t));

  102. 

  103.   /* Assign state pointer */

  104.   S->pState = pState;

  105. }

  106. 

  107. /**    

  108.  * @} end of BiquadCascadeDF1 group    

  109.  */