A bundled STM32F10x Std Periph and CMSIS library
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  1. /* ----------------------------------------------------------------------
  2. * Copyright (C) 2010-2014 ARM Limited. All rights reserved.
  3. *
  4. * $Date: 12. March 2014
  5. * $Revision: V1.4.4
  6. *
  7. * Project: CMSIS DSP Library
  8. * Title: arm_biquad_cascade_df1_32x64_init_q31.c
  9. *
  10. * Description: High precision Q31 Biquad cascade filter initialization function.
  11. *
  12. * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
  13. *
  14. * Redistribution and use in source and binary forms, with or without
  15. * modification, are permitted provided that the following conditions
  16. * are met:
  17. * - Redistributions of source code must retain the above copyright
  18. * notice, this list of conditions and the following disclaimer.
  19. * - Redistributions in binary form must reproduce the above copyright
  20. * notice, this list of conditions and the following disclaimer in
  21. * the documentation and/or other materials provided with the
  22. * distribution.
  23. * - Neither the name of ARM LIMITED nor the names of its contributors
  24. * may be used to endorse or promote products derived from this
  25. * software without specific prior written permission.
  26. *
  27. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  30. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
  31. * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  32. * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  33. * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  34. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  35. * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  36. * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
  37. * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  38. * POSSIBILITY OF SUCH DAMAGE.
  39. * -------------------------------------------------------------------- */
  40. #include "arm_math.h"
  41. /**
  42. * @ingroup groupFilters
  43. */
  44. /**
  45. * @addtogroup BiquadCascadeDF1_32x64
  46. * @{
  47. */
  48. /**
  49. * @details
  50. *
  51. * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure.
  52. * @param[in] numStages number of 2nd order stages in the filter.
  53. * @param[in] *pCoeffs points to the filter coefficients.
  54. * @param[in] *pState points to the state buffer.
  55. * @param[in] postShift Shift to be applied after the accumulator. Varies according to the coefficients format.
  56. * @return none
  57. *
  58. * <b>Coefficient and State Ordering:</b>
  59. *
  60. * \par
  61. * The coefficients are stored in the array <code>pCoeffs</code> in the following order:
  62. * <pre>
  63. * {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
  64. * </pre>
  65. * where <code>b1x</code> and <code>a1x</code> are the coefficients for the first stage,
  66. * <code>b2x</code> and <code>a2x</code> are the coefficients for the second stage,
  67. * and so on. The <code>pCoeffs</code> array contains a total of <code>5*numStages</code> values.
  68. *
  69. * \par
  70. * The <code>pState</code> points to state variables array and size of each state variable is 1.63 format.
  71. * Each Biquad stage has 4 state variables <code>x[n-1], x[n-2], y[n-1],</code> and <code>y[n-2]</code>.
  72. * The state variables are arranged in the state array as:
  73. * <pre>
  74. * {x[n-1], x[n-2], y[n-1], y[n-2]}
  75. * </pre>
  76. * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.
  77. * The state array has a total length of <code>4*numStages</code> values.
  78. * The state variables are updated after each block of data is processed; the coefficients are untouched.
  79. */
  80. void arm_biquad_cas_df1_32x64_init_q31(
  81. arm_biquad_cas_df1_32x64_ins_q31 * S,
  82. uint8_t numStages,
  83. q31_t * pCoeffs,
  84. q63_t * pState,
  85. uint8_t postShift)
  86. {
  87. /* Assign filter stages */
  88. S->numStages = numStages;
  89. /* Assign postShift to be applied to the output */
  90. S->postShift = postShift;
  91. /* Assign coefficient pointer */
  92. S->pCoeffs = pCoeffs;
  93. /* Clear state buffer and size is always 4 * numStages */
  94. memset(pState, 0, (4u * (uint32_t) numStages) * sizeof(q63_t));
  95. /* Assign state pointer */
  96. S->pState = pState;
  97. }
  98. /**
  99. * @} end of BiquadCascadeDF1_32x64 group
  100. */