A bundled STM32F10x Std Periph and CMSIS library
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  1. /* ----------------------------------------------------------------------
  2. * Copyright (C) 2010-2014 ARM Limited. All rights reserved.
  3. *
  4. * $Date: 31. July 2014
  5. * $Revision: V1.4.4
  6. *
  7. * Project: CMSIS DSP Library
  8. * Title: arm_const_structs.c
  9. *
  10. * Description: This file has constant structs that are initialized for
  11. * user convenience. For example, some can be given as
  12. * arguments to the arm_cfft_f32() function.
  13. *
  14. * Target Processor: Cortex-M4/Cortex-M3
  15. *
  16. * Redistribution and use in source and binary forms, with or without
  17. * modification, are permitted provided that the following conditions
  18. * are met:
  19. * - Redistributions of source code must retain the above copyright
  20. * notice, this list of conditions and the following disclaimer.
  21. * - Redistributions in binary form must reproduce the above copyright
  22. * notice, this list of conditions and the following disclaimer in
  23. * the documentation and/or other materials provided with the
  24. * distribution.
  25. * - Neither the name of ARM LIMITED nor the names of its contributors
  26. * may be used to endorse or promote products derived from this
  27. * software without specific prior written permission.
  28. *
  29. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  32. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
  33. * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  34. * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  35. * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  36. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  37. * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  38. * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
  39. * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  40. * POSSIBILITY OF SUCH DAMAGE.
  41. * -------------------------------------------------------------------- */
  42. #include "arm_const_structs.h"
  43. //Floating-point structs
  44. const arm_cfft_instance_f32 arm_cfft_sR_f32_len16 = {
  45. 16, twiddleCoef_16, armBitRevIndexTable16, ARMBITREVINDEXTABLE__16_TABLE_LENGTH
  46. };
  47. const arm_cfft_instance_f32 arm_cfft_sR_f32_len32 = {
  48. 32, twiddleCoef_32, armBitRevIndexTable32, ARMBITREVINDEXTABLE__32_TABLE_LENGTH
  49. };
  50. const arm_cfft_instance_f32 arm_cfft_sR_f32_len64 = {
  51. 64, twiddleCoef_64, armBitRevIndexTable64, ARMBITREVINDEXTABLE__64_TABLE_LENGTH
  52. };
  53. const arm_cfft_instance_f32 arm_cfft_sR_f32_len128 = {
  54. 128, twiddleCoef_128, armBitRevIndexTable128, ARMBITREVINDEXTABLE_128_TABLE_LENGTH
  55. };
  56. const arm_cfft_instance_f32 arm_cfft_sR_f32_len256 = {
  57. 256, twiddleCoef_256, armBitRevIndexTable256, ARMBITREVINDEXTABLE_256_TABLE_LENGTH
  58. };
  59. const arm_cfft_instance_f32 arm_cfft_sR_f32_len512 = {
  60. 512, twiddleCoef_512, armBitRevIndexTable512, ARMBITREVINDEXTABLE_512_TABLE_LENGTH
  61. };
  62. const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024 = {
  63. 1024, twiddleCoef_1024, armBitRevIndexTable1024, ARMBITREVINDEXTABLE1024_TABLE_LENGTH
  64. };
  65. const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048 = {
  66. 2048, twiddleCoef_2048, armBitRevIndexTable2048, ARMBITREVINDEXTABLE2048_TABLE_LENGTH
  67. };
  68. const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096 = {
  69. 4096, twiddleCoef_4096, armBitRevIndexTable4096, ARMBITREVINDEXTABLE4096_TABLE_LENGTH
  70. };
  71. //Fixed-point structs
  72. const arm_cfft_instance_q31 arm_cfft_sR_q31_len16 = {
  73. 16, twiddleCoef_16_q31, armBitRevIndexTable_fixed_16, ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH
  74. };
  75. const arm_cfft_instance_q31 arm_cfft_sR_q31_len32 = {
  76. 32, twiddleCoef_32_q31, armBitRevIndexTable_fixed_32, ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH
  77. };
  78. const arm_cfft_instance_q31 arm_cfft_sR_q31_len64 = {
  79. 64, twiddleCoef_64_q31, armBitRevIndexTable_fixed_64, ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH
  80. };
  81. const arm_cfft_instance_q31 arm_cfft_sR_q31_len128 = {
  82. 128, twiddleCoef_128_q31, armBitRevIndexTable_fixed_128, ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH
  83. };
  84. const arm_cfft_instance_q31 arm_cfft_sR_q31_len256 = {
  85. 256, twiddleCoef_256_q31, armBitRevIndexTable_fixed_256, ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH
  86. };
  87. const arm_cfft_instance_q31 arm_cfft_sR_q31_len512 = {
  88. 512, twiddleCoef_512_q31, armBitRevIndexTable_fixed_512, ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH
  89. };
  90. const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024 = {
  91. 1024, twiddleCoef_1024_q31, armBitRevIndexTable_fixed_1024, ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH
  92. };
  93. const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048 = {
  94. 2048, twiddleCoef_2048_q31, armBitRevIndexTable_fixed_2048, ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH
  95. };
  96. const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096 = {
  97. 4096, twiddleCoef_4096_q31, armBitRevIndexTable_fixed_4096, ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH
  98. };
  99. const arm_cfft_instance_q15 arm_cfft_sR_q15_len16 = {
  100. 16, twiddleCoef_16_q15, armBitRevIndexTable_fixed_16, ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH
  101. };
  102. const arm_cfft_instance_q15 arm_cfft_sR_q15_len32 = {
  103. 32, twiddleCoef_32_q15, armBitRevIndexTable_fixed_32, ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH
  104. };
  105. const arm_cfft_instance_q15 arm_cfft_sR_q15_len64 = {
  106. 64, twiddleCoef_64_q15, armBitRevIndexTable_fixed_64, ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH
  107. };
  108. const arm_cfft_instance_q15 arm_cfft_sR_q15_len128 = {
  109. 128, twiddleCoef_128_q15, armBitRevIndexTable_fixed_128, ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH
  110. };
  111. const arm_cfft_instance_q15 arm_cfft_sR_q15_len256 = {
  112. 256, twiddleCoef_256_q15, armBitRevIndexTable_fixed_256, ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH
  113. };
  114. const arm_cfft_instance_q15 arm_cfft_sR_q15_len512 = {
  115. 512, twiddleCoef_512_q15, armBitRevIndexTable_fixed_512, ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH
  116. };
  117. const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024 = {
  118. 1024, twiddleCoef_1024_q15, armBitRevIndexTable_fixed_1024, ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH
  119. };
  120. const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048 = {
  121. 2048, twiddleCoef_2048_q15, armBitRevIndexTable_fixed_2048, ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH
  122. };
  123. const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096 = {
  124. 4096, twiddleCoef_4096_q15, armBitRevIndexTable_fixed_4096, ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH
  125. };