A bundled STM32F10x Std Periph and CMSIS library
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  1. /* ----------------------------------------------------------------------
  2. * Copyright (C) 2010-2014 ARM Limited. All rights reserved.
  3. *
  4. * $Date: 12. March 2014
  5. * $Revision: V1.4.4
  6. *
  7. * Project: CMSIS DSP Library
  8. * Title: arm_sub_q15.c
  9. *
  10. * Description: Q15 vector subtraction.
  11. *
  12. * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
  13. *
  14. * Redistribution and use in source and binary forms, with or without
  15. * modification, are permitted provided that the following conditions
  16. * are met:
  17. * - Redistributions of source code must retain the above copyright
  18. * notice, this list of conditions and the following disclaimer.
  19. * - Redistributions in binary form must reproduce the above copyright
  20. * notice, this list of conditions and the following disclaimer in
  21. * the documentation and/or other materials provided with the
  22. * distribution.
  23. * - Neither the name of ARM LIMITED nor the names of its contributors
  24. * may be used to endorse or promote products derived from this
  25. * software without specific prior written permission.
  26. *
  27. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  30. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
  31. * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  32. * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  33. * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  34. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  35. * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  36. * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
  37. * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  38. * POSSIBILITY OF SUCH DAMAGE.
  39. * -------------------------------------------------------------------- */
  40. #include "arm_math.h"
  41. /**
  42. * @ingroup groupMath
  43. */
  44. /**
  45. * @addtogroup BasicSub
  46. * @{
  47. */
  48. /**
  49. * @brief Q15 vector subtraction.
  50. * @param[in] *pSrcA points to the first input vector
  51. * @param[in] *pSrcB points to the second input vector
  52. * @param[out] *pDst points to the output vector
  53. * @param[in] blockSize number of samples in each vector
  54. * @return none.
  55. *
  56. * <b>Scaling and Overflow Behavior:</b>
  57. * \par
  58. * The function uses saturating arithmetic.
  59. * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.
  60. */
  61. void arm_sub_q15(
  62. q15_t * pSrcA,
  63. q15_t * pSrcB,
  64. q15_t * pDst,
  65. uint32_t blockSize)
  66. {
  67. uint32_t blkCnt; /* loop counter */
  68. #ifndef ARM_MATH_CM0_FAMILY
  69. /* Run the below code for Cortex-M4 and Cortex-M3 */
  70. q31_t inA1, inA2;
  71. q31_t inB1, inB2;
  72. /*loop Unrolling */
  73. blkCnt = blockSize >> 2u;
  74. /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
  75. ** a second loop below computes the remaining 1 to 3 samples. */
  76. while(blkCnt > 0u)
  77. {
  78. /* C = A - B */
  79. /* Subtract and then store the results in the destination buffer two samples at a time. */
  80. inA1 = *__SIMD32(pSrcA)++;
  81. inA2 = *__SIMD32(pSrcA)++;
  82. inB1 = *__SIMD32(pSrcB)++;
  83. inB2 = *__SIMD32(pSrcB)++;
  84. *__SIMD32(pDst)++ = __QSUB16(inA1, inB1);
  85. *__SIMD32(pDst)++ = __QSUB16(inA2, inB2);
  86. /* Decrement the loop counter */
  87. blkCnt--;
  88. }
  89. /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
  90. ** No loop unrolling is used. */
  91. blkCnt = blockSize % 0x4u;
  92. while(blkCnt > 0u)
  93. {
  94. /* C = A - B */
  95. /* Subtract and then store the result in the destination buffer. */
  96. *pDst++ = (q15_t) __QSUB16(*pSrcA++, *pSrcB++);
  97. /* Decrement the loop counter */
  98. blkCnt--;
  99. }
  100. #else
  101. /* Run the below code for Cortex-M0 */
  102. /* Initialize blkCnt with number of samples */
  103. blkCnt = blockSize;
  104. while(blkCnt > 0u)
  105. {
  106. /* C = A - B */
  107. /* Subtract and then store the result in the destination buffer. */
  108. *pDst++ = (q15_t) __SSAT(((q31_t) * pSrcA++ - *pSrcB++), 16);
  109. /* Decrement the loop counter */
  110. blkCnt--;
  111. }
  112. #endif /* #ifndef ARM_MATH_CM0_FAMILY */
  113. }
  114. /**
  115. * @} end of BasicSub group
  116. */