A bundled STM32F10x Std Periph and CMSIS library
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  1. /* ----------------------------------------------------------------------
  2. * Copyright (C) 2010-2014 ARM Limited. All rights reserved.
  3. *
  4. * $Date: 12. March 2014
  5. * $Revision: V1.4.4
  6. *
  7. * Project: CMSIS DSP Library
  8. * Title: arm_scale_q7.c
  9. *
  10. * Description: Multiplies a Q7 vector by a scalar.
  11. *
  12. * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
  13. *
  14. * Redistribution and use in source and binary forms, with or without
  15. * modification, are permitted provided that the following conditions
  16. * are met:
  17. * - Redistributions of source code must retain the above copyright
  18. * notice, this list of conditions and the following disclaimer.
  19. * - Redistributions in binary form must reproduce the above copyright
  20. * notice, this list of conditions and the following disclaimer in
  21. * the documentation and/or other materials provided with the
  22. * distribution.
  23. * - Neither the name of ARM LIMITED nor the names of its contributors
  24. * may be used to endorse or promote products derived from this
  25. * software without specific prior written permission.
  26. *
  27. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  30. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
  31. * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  32. * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  33. * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  34. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  35. * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  36. * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
  37. * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  38. * POSSIBILITY OF SUCH DAMAGE.
  39. * -------------------------------------------------------------------- */
  40. #include "arm_math.h"
  41. /**
  42. * @ingroup groupMath
  43. */
  44. /**
  45. * @addtogroup scale
  46. * @{
  47. */
  48. /**
  49. * @brief Multiplies a Q7 vector by a scalar.
  50. * @param[in] *pSrc points to the input vector
  51. * @param[in] scaleFract fractional portion of the scale value
  52. * @param[in] shift number of bits to shift the result by
  53. * @param[out] *pDst points to the output vector
  54. * @param[in] blockSize number of samples in the vector
  55. * @return none.
  56. *
  57. * <b>Scaling and Overflow Behavior:</b>
  58. * \par
  59. * The input data <code>*pSrc</code> and <code>scaleFract</code> are in 1.7 format.
  60. * These are multiplied to yield a 2.14 intermediate result and this is shifted with saturation to 1.7 format.
  61. */
  62. void arm_scale_q7(
  63. q7_t * pSrc,
  64. q7_t scaleFract,
  65. int8_t shift,
  66. q7_t * pDst,
  67. uint32_t blockSize)
  68. {
  69. int8_t kShift = 7 - shift; /* shift to apply after scaling */
  70. uint32_t blkCnt; /* loop counter */
  71. #ifndef ARM_MATH_CM0_FAMILY
  72. /* Run the below code for Cortex-M4 and Cortex-M3 */
  73. q7_t in1, in2, in3, in4, out1, out2, out3, out4; /* Temporary variables to store input & output */
  74. /*loop Unrolling */
  75. blkCnt = blockSize >> 2u;
  76. /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
  77. ** a second loop below computes the remaining 1 to 3 samples. */
  78. while(blkCnt > 0u)
  79. {
  80. /* Reading 4 inputs from memory */
  81. in1 = *pSrc++;
  82. in2 = *pSrc++;
  83. in3 = *pSrc++;
  84. in4 = *pSrc++;
  85. /* C = A * scale */
  86. /* Scale the inputs and then store the results in the temporary variables. */
  87. out1 = (q7_t) (__SSAT(((in1) * scaleFract) >> kShift, 8));
  88. out2 = (q7_t) (__SSAT(((in2) * scaleFract) >> kShift, 8));
  89. out3 = (q7_t) (__SSAT(((in3) * scaleFract) >> kShift, 8));
  90. out4 = (q7_t) (__SSAT(((in4) * scaleFract) >> kShift, 8));
  91. /* Packing the individual outputs into 32bit and storing in
  92. * destination buffer in single write */
  93. *__SIMD32(pDst)++ = __PACKq7(out1, out2, out3, out4);
  94. /* Decrement the loop counter */
  95. blkCnt--;
  96. }
  97. /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
  98. ** No loop unrolling is used. */
  99. blkCnt = blockSize % 0x4u;
  100. while(blkCnt > 0u)
  101. {
  102. /* C = A * scale */
  103. /* Scale the input and then store the result in the destination buffer. */
  104. *pDst++ = (q7_t) (__SSAT(((*pSrc++) * scaleFract) >> kShift, 8));
  105. /* Decrement the loop counter */
  106. blkCnt--;
  107. }
  108. #else
  109. /* Run the below code for Cortex-M0 */
  110. /* Initialize blkCnt with number of samples */
  111. blkCnt = blockSize;
  112. while(blkCnt > 0u)
  113. {
  114. /* C = A * scale */
  115. /* Scale the input and then store the result in the destination buffer. */
  116. *pDst++ = (q7_t) (__SSAT((((q15_t) * pSrc++ * scaleFract) >> kShift), 8));
  117. /* Decrement the loop counter */
  118. blkCnt--;
  119. }
  120. #endif /* #ifndef ARM_MATH_CM0_FAMILY */
  121. }
  122. /**
  123. * @} end of scale group
  124. */