A bundled STM32F10x Std Periph and CMSIS library
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  1. /* ----------------------------------------------------------------------
  2. * Copyright (C) 2010-2014 ARM Limited. All rights reserved.
  3. *
  4. * $Date: 12. March 2014
  5. * $Revision: V1.4.4
  6. *
  7. * Project: CMSIS DSP Library
  8. * Title: arm_dot_prod_q31.c
  9. *
  10. * Description: Q31 dot product.
  11. *
  12. * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
  13. *
  14. * Redistribution and use in source and binary forms, with or without
  15. * modification, are permitted provided that the following conditions
  16. * are met:
  17. * - Redistributions of source code must retain the above copyright
  18. * notice, this list of conditions and the following disclaimer.
  19. * - Redistributions in binary form must reproduce the above copyright
  20. * notice, this list of conditions and the following disclaimer in
  21. * the documentation and/or other materials provided with the
  22. * distribution.
  23. * - Neither the name of ARM LIMITED nor the names of its contributors
  24. * may be used to endorse or promote products derived from this
  25. * software without specific prior written permission.
  26. *
  27. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  30. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
  31. * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  32. * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  33. * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  34. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  35. * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  36. * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
  37. * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  38. * POSSIBILITY OF SUCH DAMAGE.
  39. * -------------------------------------------------------------------- */
  40. #include "arm_math.h"
  41. /**
  42. * @ingroup groupMath
  43. */
  44. /**
  45. * @addtogroup dot_prod
  46. * @{
  47. */
  48. /**
  49. * @brief Dot product of Q31 vectors.
  50. * @param[in] *pSrcA points to the first input vector
  51. * @param[in] *pSrcB points to the second input vector
  52. * @param[in] blockSize number of samples in each vector
  53. * @param[out] *result output result returned here
  54. * @return none.
  55. *
  56. * <b>Scaling and Overflow Behavior:</b>
  57. * \par
  58. * The intermediate multiplications are in 1.31 x 1.31 = 2.62 format and these
  59. * are truncated to 2.48 format by discarding the lower 14 bits.
  60. * The 2.48 result is then added without saturation to a 64-bit accumulator in 16.48 format.
  61. * There are 15 guard bits in the accumulator and there is no risk of overflow as long as
  62. * the length of the vectors is less than 2^16 elements.
  63. * The return result is in 16.48 format.
  64. */
  65. void arm_dot_prod_q31(
  66. q31_t * pSrcA,
  67. q31_t * pSrcB,
  68. uint32_t blockSize,
  69. q63_t * result)
  70. {
  71. q63_t sum = 0; /* Temporary result storage */
  72. uint32_t blkCnt; /* loop counter */
  73. #ifndef ARM_MATH_CM0_FAMILY
  74. /* Run the below code for Cortex-M4 and Cortex-M3 */
  75. q31_t inA1, inA2, inA3, inA4;
  76. q31_t inB1, inB2, inB3, inB4;
  77. /*loop Unrolling */
  78. blkCnt = blockSize >> 2u;
  79. /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
  80. ** a second loop below computes the remaining 1 to 3 samples. */
  81. while(blkCnt > 0u)
  82. {
  83. /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
  84. /* Calculate dot product and then store the result in a temporary buffer. */
  85. inA1 = *pSrcA++;
  86. inA2 = *pSrcA++;
  87. inA3 = *pSrcA++;
  88. inA4 = *pSrcA++;
  89. inB1 = *pSrcB++;
  90. inB2 = *pSrcB++;
  91. inB3 = *pSrcB++;
  92. inB4 = *pSrcB++;
  93. sum += ((q63_t) inA1 * inB1) >> 14u;
  94. sum += ((q63_t) inA2 * inB2) >> 14u;
  95. sum += ((q63_t) inA3 * inB3) >> 14u;
  96. sum += ((q63_t) inA4 * inB4) >> 14u;
  97. /* Decrement the loop counter */
  98. blkCnt--;
  99. }
  100. /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
  101. ** No loop unrolling is used. */
  102. blkCnt = blockSize % 0x4u;
  103. #else
  104. /* Run the below code for Cortex-M0 */
  105. /* Initialize blkCnt with number of samples */
  106. blkCnt = blockSize;
  107. #endif /* #ifndef ARM_MATH_CM0_FAMILY */
  108. while(blkCnt > 0u)
  109. {
  110. /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
  111. /* Calculate dot product and then store the result in a temporary buffer. */
  112. sum += ((q63_t) * pSrcA++ * *pSrcB++) >> 14u;
  113. /* Decrement the loop counter */
  114. blkCnt--;
  115. }
  116. /* Store the result in the destination buffer in 16.48 format */
  117. *result = sum;
  118. }
  119. /**
  120. * @} end of dot_prod group
  121. */