A bundled STM32F10x Std Periph and CMSIS library
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  1. <html>
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  3. <title>CMSIS Changes</title>
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  73. <h1>Changes to CMSIS version V1.20</h1>
  74. <hr>
  75. <h2>1. Removed CMSIS Middelware packages</h2>
  76. <p>
  77. CMSIS Middleware is on hold from ARM side until a agreement between all CMSIS partners is found.
  78. </p>
  79. <h2>2. SystemFrequency renamed to SystemCoreClock</h2>
  80. <p>
  81. The variable name <strong>SystemCoreClock</strong> is more precise than <strong>SystemFrequency</strong>
  82. because the variable holds the clock value at which the core is running.
  83. </p>
  84. <h2>3. Changed startup concept</h2>
  85. <p>
  86. The old startup concept (calling SystemInit_ExtMemCtl from startup file and calling SystemInit
  87. from main) has the weakness that it does not work for controllers which need a already
  88. configuerd clock system to configure the external memory controller.
  89. </p>
  90. <h3>Changed startup concept</h3>
  91. <ul>
  92. <li>
  93. SystemInit() is called from startup file before <strong>premain</strong>.
  94. </li>
  95. <li>
  96. <strong>SystemInit()</strong> configures the clock system and also configures
  97. an existing external memory controller.
  98. </li>
  99. <li>
  100. <strong>SystemInit()</strong> must not use global variables.
  101. </li>
  102. <li>
  103. <strong>SystemCoreClock</strong> is initialized with a correct predefined value.
  104. </li>
  105. <li>
  106. Additional function <strong>void SystemCoreClockUpdate (void)</strong> is provided.<br>
  107. <strong>SystemCoreClockUpdate()</strong> updates the variable <strong>SystemCoreClock</strong>
  108. and must be called whenever the core clock is changed.<br>
  109. <strong>SystemCoreClockUpdate()</strong> evaluates the clock register settings and calculates
  110. the current core clock.
  111. </li>
  112. </ul>
  113. <h2>4. Advanced Debug Functions</h2>
  114. <p>
  115. ITM communication channel is only capable for OUT direction. To allow also communication for
  116. IN direction a simple concept is provided.
  117. </p>
  118. <ul>
  119. <li>
  120. Global variable <strong>volatile int ITM_RxBuffer</strong> used for IN data.
  121. </li>
  122. <li>
  123. Function <strong>int ITM_CheckChar (void)</strong> checks if a new character is available.
  124. </li>
  125. <li>
  126. Function <strong>int ITM_ReceiveChar (void)</strong> retrieves the new character.
  127. </li>
  128. </ul>
  129. <p>
  130. For detailed explanation see file <strong>CMSIS debug support.htm</strong>.
  131. </p>
  132. <h2>5. Core Register Bit Definitions</h2>
  133. <p>
  134. Files core_cm3.h and core_cm0.h contain now bit definitions for Core Registers. The name for the
  135. defines correspond with the Cortex-M Technical Reference Manual.
  136. </p>
  137. <p>
  138. e.g. SysTick structure with bit definitions
  139. </p>
  140. <pre>
  141. /** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick
  142. memory mapped structure for SysTick
  143. @{
  144. */
  145. typedef struct
  146. {
  147. __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */
  148. __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */
  149. __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */
  150. __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */
  151. } SysTick_Type;
  152. /* SysTick Control / Status Register Definitions */
  153. #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
  154. #define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
  155. #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
  156. #define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
  157. #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
  158. #define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
  159. #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
  160. #define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
  161. /* SysTick Reload Register Definitions */
  162. #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
  163. #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
  164. /* SysTick Current Register Definitions */
  165. #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
  166. #define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
  167. /* SysTick Calibration Register Definitions */
  168. #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
  169. #define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
  170. #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
  171. #define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
  172. #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
  173. #define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
  174. /*@}*/ /* end of group CMSIS_CM3_SysTick */</pre>
  175. <h2>7. DoxyGen Tags</h2>
  176. <p>
  177. DoxyGen tags in files core_cm3.[c,h] and core_cm0.[c,h] are reworked to create proper documentation
  178. using DoxyGen.
  179. </p>
  180. <h2>8. Folder Structure</h2>
  181. <p>
  182. The folder structure is changed to differentiate the single support packages.
  183. </p>
  184. <ul>
  185. <li>CM0</li>
  186. <li>CM3
  187. <ul>
  188. <li>CoreSupport</li>
  189. <li>DeviceSupport</li>
  190. <ul>
  191. <li>Vendor
  192. <ul>
  193. <li>Device
  194. <ul>
  195. <li>Startup
  196. <ul>
  197. <li>Toolchain</li>
  198. <li>Toolchain</li>
  199. <li>...</li>
  200. </ul>
  201. </li>
  202. </ul>
  203. </li>
  204. <li>Device</li>
  205. <li>...</li>
  206. </ul>
  207. </li>
  208. <li>Vendor</li>
  209. <li>...</li>
  210. </ul>
  211. </li>
  212. <li>Example
  213. <ul>
  214. <li>Toolchain
  215. <ul>
  216. <li>Device</li>
  217. <li>Device</li>
  218. <li>...</li>
  219. </ul>
  220. </li>
  221. <li>Toolchain</li>
  222. <li>...</li>
  223. </ul>
  224. </li>
  225. </ul>
  226. </li>
  227. <li>Documentation</li>
  228. </ul>
  229. <h2>9. Open Points</h2>
  230. <p>
  231. Following points need to be clarified and solved:
  232. </p>
  233. <ul>
  234. <li>
  235. <p>
  236. Equivalent C and Assembler startup files.
  237. </p>
  238. <p>
  239. Is there a need for having C startup files although assembler startup files are
  240. very efficient and do not need to be changed?
  241. <p/>
  242. </li>
  243. <li>
  244. <p>
  245. Placing of HEAP in external RAM.
  246. </p>
  247. <p>
  248. It must be possible to place HEAP in external RAM if the device supports an
  249. external memory controller.
  250. </p>
  251. </li>
  252. <li>
  253. <p>
  254. Placing of STACK /HEAP.
  255. </p>
  256. <p>
  257. STACK should always be placed at the end of internal RAM.
  258. </p>
  259. <p>
  260. If HEAP is placed in internal RAM than it should be placed after RW ZI section.
  261. </p>
  262. </li>
  263. <li>
  264. <p>
  265. Removing core_cm3.c and core_cm0.c.
  266. </p>
  267. <p>
  268. On a long term the functions in core_cm3.c and core_cm0.c must be replaced with
  269. appropriate compiler intrinsics.
  270. </p>
  271. </li>
  272. </ul>
  273. <h2>10. Limitations</h2>
  274. <p>
  275. The following limitations are not covered with the current CMSIS version:
  276. </p>
  277. <ul>
  278. <li>
  279. No <strong>C startup files</strong> for ARM toolchain are provided.
  280. </li>
  281. <li>
  282. No <strong>C startup files</strong> for GNU toolchain are provided.
  283. </li>
  284. <li>
  285. No <strong>C startup files</strong> for IAR toolchain are provided.
  286. </li>
  287. <li>
  288. No <strong>Tasking</strong> projects are provided yet.
  289. </li>
  290. </ul>