Init commit of bundled StdPeriph-CMSIS library
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;/**************************************************************************//**
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; * @file startup_ARMCM0.s
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; * @brief CMSIS Core Device Startup File for
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; * ARMCM0 Device Series
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; * @version V1.07
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; * @date 30. January 2012
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; *
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; * @note
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; * Copyright (C) 2012 ARM Limited. All rights reserved.
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; *
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; * @par
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; * ARM Limited (ARM) is supplying this software for use with Cortex-M
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; * processor based microcontrollers. This file can be freely distributed
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; * within development tools that are supporting such ARM based processors.
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; *
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; * @par
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; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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; *
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; ******************************************************************************/
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;
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; The modules in this file are included in the libraries, and may be replaced
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; by any user-defined modules that define the PUBLIC symbol _program_start or
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; a user defined start symbol.
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; To override the cstartup defined in the library, simply add your modified
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; version to the workbench project.
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;
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; The vector table is normally located at address 0.
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; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
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; The name "__vector_table" has special meaning for C-SPY:
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; it is where the SP start value is found, and the NVIC vector
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; table register (VTOR) is initialized to this address if != 0.
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;
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; Cortex-M version
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;
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MODULE ?cstartup
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;; Forward declaration of sections.
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SECTION CSTACK:DATA:NOROOT(3)
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SECTION .intvec:CODE:NOROOT(2)
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EXTERN __iar_program_start
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EXTERN SystemInit
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PUBLIC __vector_table
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PUBLIC __vector_table_0x1c
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PUBLIC __Vectors
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PUBLIC __Vectors_End
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PUBLIC __Vectors_Size
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DATA
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__vector_table
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DCD sfe(CSTACK)
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DCD Reset_Handler
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DCD NMI_Handler
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DCD HardFault_Handler
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DCD 0
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DCD 0
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DCD 0
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__vector_table_0x1c
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DCD 0
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DCD 0
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DCD 0
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DCD 0
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DCD SVC_Handler
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DCD 0
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DCD 0
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DCD PendSV_Handler
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DCD SysTick_Handler
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; External Interrupts
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DCD WDT_IRQHandler ; 0: Watchdog Timer
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DCD RTC_IRQHandler ; 1: Real Time Clock
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DCD TIM0_IRQHandler ; 2: Timer0 / Timer1
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DCD TIM2_IRQHandler ; 3: Timer2 / Timer3
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DCD MCIA_IRQHandler ; 4: MCIa
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DCD MCIB_IRQHandler ; 5: MCIb
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DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA
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DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA
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DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA
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DCD UART4_IRQHandler ; 9: UART4 - not connected
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DCD AACI_IRQHandler ; 10: AACI / AC97
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DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt
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DCD ENET_IRQHandler ; 12: Ethernet
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DCD USBDC_IRQHandler ; 13: USB Device
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DCD USBHC_IRQHandler ; 14: USB Host Controller
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DCD CHLCD_IRQHandler ; 15: Character LCD
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DCD FLEXRAY_IRQHandler ; 16: Flexray
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DCD CAN_IRQHandler ; 17: CAN
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DCD LIN_IRQHandler ; 18: LIN
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DCD I2C_IRQHandler ; 19: I2C ADC/DAC
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DCD 0 ; 20: Reserved
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DCD 0 ; 21: Reserved
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DCD 0 ; 22: Reserved
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DCD 0 ; 23: Reserved
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DCD 0 ; 24: Reserved
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DCD 0 ; 25: Reserved
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DCD 0 ; 26: Reserved
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DCD 0 ; 27: Reserved
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DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD
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DCD 0 ; 29: Reserved - CPU FPGA
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DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA
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DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA
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__Vectors_End
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__Vectors EQU __vector_table
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__Vectors_Size EQU __Vectors_End - __Vectors
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;
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;; Default interrupt handlers.
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;;
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THUMB
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PUBWEAK Reset_Handler
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SECTION .text:CODE:REORDER(2)
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Reset_Handler
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__iar_program_start
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BX R0
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PUBWEAK NMI_Handler
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SECTION .text:CODE:REORDER(1)
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NMI_Handler
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B NMI_Handler
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PUBWEAK HardFault_Handler
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SECTION .text:CODE:REORDER(1)
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HardFault_Handler
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B HardFault_Handler
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PUBWEAK SVC_Handler
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SECTION .text:CODE:REORDER(1)
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SVC_Handler
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B SVC_Handler
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PUBWEAK PendSV_Handler
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SECTION .text:CODE:REORDER(1)
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PendSV_Handler
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B PendSV_Handler
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PUBWEAK SysTick_Handler
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SECTION .text:CODE:REORDER(1)
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SysTick_Handler
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B SysTick_Handler
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PUBWEAK WDT_IRQHandler
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SECTION .text:CODE:REORDER(1)
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WDT_IRQHandler
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B WDT_IRQHandler
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PUBWEAK RTC_IRQHandler
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SECTION .text:CODE:REORDER(1)
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RTC_IRQHandler
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B RTC_IRQHandler
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PUBWEAK TIM0_IRQHandler
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SECTION .text:CODE:REORDER(1)
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TIM0_IRQHandler
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B TIM0_IRQHandler
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PUBWEAK TIM2_IRQHandler
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SECTION .text:CODE:REORDER(1)
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TIM2_IRQHandler
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B TIM2_IRQHandler
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PUBWEAK MCIA_IRQHandler
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SECTION .text:CODE:REORDER(1)
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MCIA_IRQHandler
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B MCIA_IRQHandler
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PUBWEAK MCIB_IRQHandler
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SECTION .text:CODE:REORDER(1)
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MCIB_IRQHandler
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B MCIB_IRQHandler
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PUBWEAK UART0_IRQHandler
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SECTION .text:CODE:REORDER(1)
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UART0_IRQHandler
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B UART0_IRQHandler
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PUBWEAK UART1_IRQHandler
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SECTION .text:CODE:REORDER(1)
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UART1_IRQHandler
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B UART1_IRQHandler
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PUBWEAK UART2_IRQHandler
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SECTION .text:CODE:REORDER(1)
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UART2_IRQHandler
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B UART2_IRQHandler
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PUBWEAK UART4_IRQHandler
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SECTION .text:CODE:REORDER(1)
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UART4_IRQHandler
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B UART4_IRQHandler
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PUBWEAK AACI_IRQHandler
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SECTION .text:CODE:REORDER(1)
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AACI_IRQHandler
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B AACI_IRQHandler
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PUBWEAK CLCD_IRQHandler
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SECTION .text:CODE:REORDER(1)
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CLCD_IRQHandler
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B CLCD_IRQHandler
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PUBWEAK ENET_IRQHandler
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SECTION .text:CODE:REORDER(1)
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ENET_IRQHandler
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B ENET_IRQHandler
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PUBWEAK USBDC_IRQHandler
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SECTION .text:CODE:REORDER(1)
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USBDC_IRQHandler
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B USBDC_IRQHandler
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PUBWEAK USBHC_IRQHandler
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SECTION .text:CODE:REORDER(1)
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USBHC_IRQHandler
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B USBHC_IRQHandler
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PUBWEAK CHLCD_IRQHandler
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SECTION .text:CODE:REORDER(1)
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CHLCD_IRQHandler
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B CHLCD_IRQHandler
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PUBWEAK FLEXRAY_IRQHandler
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SECTION .text:CODE:REORDER(1)
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FLEXRAY_IRQHandler
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B FLEXRAY_IRQHandler
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PUBWEAK CAN_IRQHandler
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SECTION .text:CODE:REORDER(1)
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CAN_IRQHandler
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B CAN_IRQHandler
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PUBWEAK LIN_IRQHandler
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SECTION .text:CODE:REORDER(1)
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LIN_IRQHandler
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B LIN_IRQHandler
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PUBWEAK I2C_IRQHandler
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SECTION .text:CODE:REORDER(1)
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I2C_IRQHandler
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B I2C_IRQHandler
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PUBWEAK CPU_CLCD_IRQHandler
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SECTION .text:CODE:REORDER(1)
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CPU_CLCD_IRQHandler
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B CPU_CLCD_IRQHandler
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PUBWEAK UART3_IRQHandler
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SECTION .text:CODE:REORDER(1)
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UART3_IRQHandler
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B UART3_IRQHandler
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PUBWEAK SPI_IRQHandler
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SECTION .text:CODE:REORDER(1)
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SPI_IRQHandler
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B SPI_IRQHandler
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END
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