A bundled STM32F10x Std Periph and CMSIS library
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ARMSC300.h 14 KiB

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  1. /**************************************************************************//**
  2. * @file ARMSC300.h
  3. * @brief CMSIS Core Peripheral Access Layer Header File for
  4. * ARMSC300 Device Series
  5. * @version V1.07
  6. * @date 30. January 2012
  7. *
  8. * @note
  9. * Copyright (C) 2012 ARM Limited. All rights reserved.
  10. *
  11. * @par
  12. * ARM Limited (ARM) is supplying this software for use with Cortex-M
  13. * processor based microcontrollers. This file can be freely distributed
  14. * within development tools that are supporting such ARM based processors.
  15. *
  16. * @par
  17. * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
  18. * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
  19. * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
  20. * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
  21. * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
  22. *
  23. ******************************************************************************/
  24. #ifndef ARMSC300_H
  25. #define ARMSC300_H
  26. #ifdef __cplusplus
  27. extern "C" {
  28. #endif
  29. /* ------------------------- Interrupt Number Definition ------------------------ */
  30. typedef enum IRQn
  31. {
  32. /* --------------------- SC300 Processor Exceptions Numbers --------------------- */
  33. NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
  34. HardFault_IRQn = -13, /*!< 3 HardFault Interrupt */
  35. MemoryManagement_IRQn = -12, /*!< 4 Memory Management Interrupt */
  36. BusFault_IRQn = -11, /*!< 5 Bus Fault Interrupt */
  37. UsageFault_IRQn = -10, /*!< 6 Usage Fault Interrupt */
  38. SVCall_IRQn = -5, /*!< 11 SV Call Interrupt */
  39. DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor Interrupt */
  40. PendSV_IRQn = -2, /*!< 14 Pend SV Interrupt */
  41. SysTick_IRQn = -1, /*!< 15 System Tick Interrupt */
  42. /* --------------------- ARMSC300 Specific Interrupt Numbers -------------------- */
  43. WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
  44. RTC_IRQn = 1, /*!< Real Time Clock Interrupt */
  45. TIM0_IRQn = 2, /*!< Timer0 / Timer1 Interrupt */
  46. TIM2_IRQn = 3, /*!< Timer2 / Timer3 Interrupt */
  47. MCIA_IRQn = 4, /*!< MCIa Interrupt */
  48. MCIB_IRQn = 5, /*!< MCIb Interrupt */
  49. UART0_IRQn = 6, /*!< UART0 Interrupt */
  50. UART1_IRQn = 7, /*!< UART1 Interrupt */
  51. UART2_IRQn = 8, /*!< UART2 Interrupt */
  52. UART4_IRQn = 9, /*!< UART4 Interrupt */
  53. AACI_IRQn = 10, /*!< AACI / AC97 Interrupt */
  54. CLCD_IRQn = 11, /*!< CLCD Combined Interrupt */
  55. ENET_IRQn = 12, /*!< Ethernet Interrupt */
  56. USBDC_IRQn = 13, /*!< USB Device Interrupt */
  57. USBHC_IRQn = 14, /*!< USB Host Controller Interrupt */
  58. CHLCD_IRQn = 15, /*!< Character LCD Interrupt */
  59. FLEXRAY_IRQn = 16, /*!< Flexray Interrupt */
  60. CAN_IRQn = 17, /*!< CAN Interrupt */
  61. LIN_IRQn = 18, /*!< LIN Interrupt */
  62. I2C_IRQn = 19, /*!< I2C ADC/DAC Interrupt */
  63. CPU_CLCD_IRQn = 28, /*!< CPU CLCD Combined Interrupt */
  64. UART3_IRQn = 30, /*!< UART3 Interrupt */
  65. SPI_IRQn = 31, /*!< SPI Touchscreen Interrupt */
  66. } IRQn_Type;
  67. /* ================================================================================ */
  68. /* ================ Processor and Core Peripheral Section ================ */
  69. /* ================================================================================ */
  70. /* -------- Configuration of the Cortex-M4 Processor and Core Peripherals ------- */
  71. #define __SC300_REV 0x0000 /*!< Core revision r0p0 */
  72. #define __MPU_PRESENT 1 /*!< MPU present or not */
  73. #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
  74. #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
  75. #include <core_SC300.h> /* Processor and core peripherals */
  76. #include "system_ARMSC300.h" /* System Header */
  77. /* ================================================================================ */
  78. /* ================ Device Specific Peripheral Section ================ */
  79. /* ================================================================================ */
  80. /* ------------------- Start of section using anonymous unions ------------------ */
  81. #if defined(__CC_ARM)
  82. #pragma push
  83. #pragma anon_unions
  84. #elif defined(__ICCARM__)
  85. #pragma language=extended
  86. #elif defined(__GNUC__)
  87. /* anonymous unions are enabled by default */
  88. #elif defined(__TMS470__)
  89. /* anonymous unions are enabled by default */
  90. #elif defined(__TASKING__)
  91. #pragma warning 586
  92. #else
  93. #warning Not supported compiler type
  94. #endif
  95. /* ================================================================================ */
  96. /* ================ CPU FPGA System (CPU_SYS) ================ */
  97. /* ================================================================================ */
  98. typedef struct
  99. {
  100. __I uint32_t ID; /* Offset: 0x000 (R/ ) Board and FPGA Identifier */
  101. __IO uint32_t MEMCFG; /* Offset: 0x004 (R/W) Remap and Alias Memory Control */
  102. __I uint32_t SW; /* Offset: 0x008 (R/ ) Switch States */
  103. __IO uint32_t LED; /* Offset: 0x00C (R/W) LED Output States */
  104. __I uint32_t TS; /* Offset: 0x010 (R/ ) Touchscreen Register */
  105. __IO uint32_t CTRL1; /* Offset: 0x014 (R/W) Misc Control Functions */
  106. uint32_t RESERVED0[2];
  107. __IO uint32_t CLKCFG; /* Offset: 0x020 (R/W) System Clock Configuration */
  108. __IO uint32_t WSCFG; /* Offset: 0x024 (R/W) Flash Waitstate Configuration */
  109. __IO uint32_t CPUCFG; /* Offset: 0x028 (R/W) Processor Configuration */
  110. uint32_t RESERVED1[3];
  111. __IO uint32_t BASE; /* Offset: 0x038 (R/W) ROM Table base Address */
  112. __IO uint32_t ID2; /* Offset: 0x03C (R/W) Secondary Identification Register */
  113. } ARM_CPU_SYS_TypeDef;
  114. /* ================================================================================ */
  115. /* ================ DUT FPGA System (DUT_SYS) ================ */
  116. /* ================================================================================ */
  117. typedef struct
  118. {
  119. __I uint32_t ID; /* Offset: 0x000 (R/ ) Board and FPGA Identifier */
  120. __IO uint32_t PERCFG; /* Offset: 0x004 (R/W) Peripheral Control Signals */
  121. __I uint32_t SW; /* Offset: 0x008 (R/ ) Switch States */
  122. __IO uint32_t LED; /* Offset: 0x00C (R/W) LED Output States */
  123. __IO uint32_t SEG7; /* Offset: 0x010 (R/W) 7-segment LED Output States */
  124. __I uint32_t CNT25MHz; /* Offset: 0x014 (R/ ) Freerunning counter incrementing at 25MHz */
  125. __I uint32_t CNT100Hz; /* Offset: 0x018 (R/ ) Freerunning counter incrementing at 100Hz */
  126. } ARM_DUT_SYS_TypeDef;
  127. /* ================================================================================ */
  128. /* ================ Timer (TIM) ================ */
  129. /* ================================================================================ */
  130. typedef struct
  131. {
  132. __IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */
  133. __I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
  134. __IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */
  135. __O uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */
  136. __I uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */
  137. __I uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */
  138. __IO uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */
  139. uint32_t RESERVED0[1];
  140. __IO uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */
  141. __I uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */
  142. __IO uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */
  143. __O uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */
  144. __I uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */
  145. __I uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */
  146. __IO uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */
  147. } ARM_TIM_TypeDef;
  148. /* ================================================================================ */
  149. /* ============== Universal Asyncronous Receiver / Transmitter (UART) ============= */
  150. /* ================================================================================ */
  151. typedef struct
  152. {
  153. __IO uint32_t DR; /* Offset: 0x000 (R/W) Data */
  154. union {
  155. __I uint32_t RSR; /* Offset: 0x000 (R/ ) Receive Status */
  156. __O uint32_t ECR; /* Offset: 0x000 ( /W) Error Clear */
  157. };
  158. uint32_t RESERVED0[4];
  159. __IO uint32_t FR; /* Offset: 0x018 (R/W) Flags */
  160. uint32_t RESERVED1[1];
  161. __IO uint32_t ILPR; /* Offset: 0x020 (R/W) IrDA Low-power Counter */
  162. __IO uint32_t IBRD; /* Offset: 0x024 (R/W) Interger Baud Rate */
  163. __IO uint32_t FBRD; /* Offset: 0x028 (R/W) Fractional Baud Rate */
  164. __IO uint32_t LCR_H; /* Offset: 0x02C (R/W) Line Control */
  165. __IO uint32_t CR; /* Offset: 0x030 (R/W) Control */
  166. __IO uint32_t IFLS; /* Offset: 0x034 (R/W) Interrupt FIFO Level Select */
  167. __IO uint32_t IMSC; /* Offset: 0x038 (R/W) Interrupt Mask Set / Clear */
  168. __IO uint32_t RIS; /* Offset: 0x03C (R/W) Raw Interrupt Status */
  169. __IO uint32_t MIS; /* Offset: 0x040 (R/W) Masked Interrupt Status */
  170. __O uint32_t ICR; /* Offset: 0x044 ( /W) Interrupt Clear */
  171. __IO uint32_t DMACR; /* Offset: 0x048 (R/W) DMA Control */
  172. } ARM_UART_TypeDef;
  173. /* -------------------- End of section using anonymous unions ------------------- */
  174. #if defined(__CC_ARM)
  175. #pragma pop
  176. #elif defined(__ICCARM__)
  177. /* leave anonymous unions enabled */
  178. #elif defined(__GNUC__)
  179. /* anonymous unions are enabled by default */
  180. #elif defined(__TMS470__)
  181. /* anonymous unions are enabled by default */
  182. #elif defined(__TASKING__)
  183. #pragma warning restore
  184. #else
  185. #warning Not supported compiler type
  186. #endif
  187. /* ================================================================================ */
  188. /* ================ Peripheral memory map ================ */
  189. /* ================================================================================ */
  190. /* -------------------------- CPU FPGA memory map ------------------------------- */
  191. #define ARM_FLASH_BASE (0x00000000UL)
  192. #define ARM_RAM_BASE (0x20000000UL)
  193. #define ARM_RAM_FPGA_BASE (0x1EFF0000UL)
  194. #define ARM_CPU_CFG_BASE (0xDFFF0000UL)
  195. #define ARM_CPU_SYS_BASE (ARM_CPU_CFG_BASE + 0x00000)
  196. #define ARM_UART3_BASE (ARM_CPU_CFG_BASE + 0x05000)
  197. /* -------------------------- DUT FPGA memory map ------------------------------- */
  198. #define ARM_APB_BASE (0x40000000UL)
  199. #define ARM_AHB_BASE (0x4FF00000UL)
  200. #define ARM_DMC_BASE (0x60000000UL)
  201. #define ARM_SMC_BASE (0xA0000000UL)
  202. #define ARM_TIM0_BASE (ARM_APB_BASE + 0x02000)
  203. #define ARM_TIM2_BASE (ARM_APB_BASE + 0x03000)
  204. #define ARM_DUT_SYS_BASE (ARM_APB_BASE + 0x04000)
  205. #define ARM_UART0_BASE (ARM_APB_BASE + 0x06000)
  206. #define ARM_UART1_BASE (ARM_APB_BASE + 0x07000)
  207. #define ARM_UART2_BASE (ARM_APB_BASE + 0x08000)
  208. #define ARM_UART4_BASE (ARM_APB_BASE + 0x09000)
  209. /* ================================================================================ */
  210. /* ================ Peripheral declaration ================ */
  211. /* ================================================================================ */
  212. /* -------------------------- CPU FPGA Peripherals ------------------------------ */
  213. #define ARM_CPU_SYS ((ARM_CPU_SYS_TypeDef *) ARM_CPU_SYS_BASE)
  214. #define ARM_UART3 (( ARM_UART_TypeDef *) ARM_UART3_BASE)
  215. /* -------------------------- DUT FPGA Peripherals ------------------------------ */
  216. #define ARM_DUT_SYS ((ARM_DUT_SYS_TypeDef *) ARM_DUT_SYS_BASE)
  217. #define ARM_TIM0 (( ARM_TIM_TypeDef *) ARM_TIM0_BASE)
  218. #define ARM_TIM2 (( ARM_TIM_TypeDef *) ARM_TIM2_BASE)
  219. #define ARM_UART0 (( ARM_UART_TypeDef *) ARM_UART0_BASE)
  220. #define ARM_UART1 (( ARM_UART_TypeDef *) ARM_UART1_BASE)
  221. #define ARM_UART2 (( ARM_UART_TypeDef *) ARM_UART2_BASE)
  222. #define ARM_UART4 (( ARM_UART_TypeDef *) ARM_UART4_BASE)
  223. #ifdef __cplusplus
  224. }
  225. #endif
  226. #endif /* ARMSC300_H */