Assignment 3: PCB design

2020-06-14 20:12:35 +03:00
parent 0fdf4330f7
commit 7d20f156e1
12 changed files with 1172 additions and 0 deletions
@@ -7,3 +7,6 @@
 [submodule "assignment_2/Libraries/STM32CubeF4"]
 	path = assignment_2/Libraries/STM32CubeF4
 	url = https://github.com/hoo2/STM32CubeF4.git
 [submodule "assignment_3/thermostat_shield/AltiumLib"]
 	path = assignment_3/thermostat_shield/AltiumLib
 	url = git@gitlab.com:hoo2/altium-lib.git
@@ -0,0 +1,3 @@
 History/
 __Previews/
 Project\ Logs\ for\ Thermostat/
@@ -0,0 +1,2 @@
 Record=TopLevelDocument|FileName=Main.SchDoc
 Record=SheetSymbol|Record=SheetSymbol|SourceDocument=Main.SchDoc|Designator=R|SchDesignator=R|FileName=Relay.SchDoc|SymbolType=Normal|RawFileName=Relay.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
		`@@ -0,0 +1,2 @@`
							`Record=TopLevelDocument\|FileName=Main.SchDoc`
							`Record=SheetSymbol\|Record=SheetSymbol\|SourceDocument=Main.SchDoc\|Designator=R\|SchDesignator=R\|FileName=Relay.SchDoc\|SymbolType=Normal\|RawFileName=Relay.SchDoc\|DesignItemId= \|SourceLibraryName= \|ObjectKind=Sheet Symbol\|RevisionGUID= \|ItemGUID= \|VaultGUID=`