Assignment 3: PCB design

2020-06-14 20:12:35 +03:00
parent 0fdf4330f7
commit 7d20f156e1
12 changed files with 1172 additions and 0 deletions
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+Record=TopLevelDocument|FileName=Main.SchDoc
+Record=SheetSymbol|Record=SheetSymbol|SourceDocument=Main.SchDoc|Designator=R|SchDesignator=R|FileName=Relay.SchDoc|SymbolType=Normal|RawFileName=Relay.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=