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HWDigSys-II
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Christos Choutouridis
bca45ad4b6
Release version
2025-06-15 22:45:59 +03:00
Compulsory coursework-2025-20250609
Init commit
2025-06-09 22:46:39 +03:00
report
Minor changes
2025-06-15 22:42:23 +03:00
sim
3 stage pipeline and top test bench
2025-06-15 20:21:30 +03:00
src
Minor changes
2025-06-15 22:42:23 +03:00
.gitignore
Init commit
2025-06-09 22:46:39 +03:00
Choutouridis_8997.zip
Release version
2025-06-15 22:45:59 +03:00
fp_mult_top.sv
3 stage pipeline and top test bench
2025-06-15 20:21:30 +03:00
fpu_mult.mpf
Minor changes
2025-06-15 22:42:23 +03:00
lab_coursework_2025.pdf
Init commit
2025-06-09 22:46:39 +03:00
描述
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4.1
MiB
Languages
SystemVerilog
65%
TeX
35%