72 lines
2.3 KiB
Systemverilog
72 lines
2.3 KiB
Systemverilog
`timescale 1ns/1ps
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module normalize_mult_tb;
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logic [47:0] mantissa_in;
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logic [9:0] exponent_in;
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logic [22:0] mantissa_out;
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logic [9:0] exponent_out;
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logic guard_bit, sticky_bit;
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normalize_mult dut (
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.mantissa_in(mantissa_in),
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.exponent_in(exponent_in),
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.mantissa_out(mantissa_out),
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.exponent_out(exponent_out),
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.guard_bit(guard_bit),
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.sticky_bit(sticky_bit)
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);
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initial begin
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integer i;
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logic [47:0] mantissa_inputs [8];
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logic [9:0] exponent_inputs [8];
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logic [22:0] exp_mantissas [8];
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logic [9:0] exp_exponents [8];
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logic exp_guard [8];
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logic exp_sticky [8];
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string result;
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$display("Starting normalize_mult test...\n");
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mantissa_inputs[0] = 48'hC40000800000; exponent_inputs[0] = 130; exp_mantissas[0] = 23'h440000; exp_exponents[0] = 131; exp_guard[0] = 1; exp_sticky[0] = 0;
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mantissa_inputs[1] = 48'h440000000080; exponent_inputs[1] = 130; exp_mantissas[1] = 23'h080000; exp_exponents[1] = 130; exp_guard[1] = 0; exp_sticky[1] = 1;
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mantissa_inputs[2] = 48'h440000400080; exponent_inputs[2] = 130; exp_mantissas[2] = 23'h080000; exp_exponents[2] = 130; exp_guard[2] = 1; exp_sticky[2] = 1;
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for (i = 0; i < 3; i++) begin
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mantissa_in = mantissa_inputs[i];
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exponent_in = exponent_inputs[i];
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#5;
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if (mantissa_out === exp_mantissas[i] &&
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exponent_out === exp_exponents[i] &&
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guard_bit === exp_guard[i] &&
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sticky_bit === exp_sticky[i])
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result = "PASS";
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else
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result = "FAIL";
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$display("[%0d] IN=%h | EXP: mant=%h exp=%0d G=%0b S=%0b | OUT: mant=%h exp=%0d G=%0b S=%0b => %s",
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i,
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mantissa_inputs[i],
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exp_mantissas[i],
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exp_exponents[i],
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exp_guard[i],
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exp_sticky[i],
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mantissa_out,
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exponent_out,
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guard_bit,
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sticky_bit,
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result
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);
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end
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$display("\nFinished normalize_mult test.");
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$stop;
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end
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endmodule
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