90 lines
3.0 KiB
Systemverilog
Executable File
90 lines
3.0 KiB
Systemverilog
Executable File
// sim/fp_mult_top_tb.sv
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`timescale 1ns/1ps
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module fp_mult_top_tb;
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logic [31:0] a, b, z;
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logic [2:0] rnd;
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logic [7:0] status;
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logic clk = 0, rst = 1;
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// DUT
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fp_mult_top dut (
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.a(a),
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.b(b),
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.rnd(rnd),
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.z(z),
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.status(status),
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.clk(clk),
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.rst(rst)
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);
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// Clock generation
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always #1 rst = 1;
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always #5 clk = ~clk;
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typedef struct {
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logic [31:0] a;
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logic [31:0] b;
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logic [31:0] expected;
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string desc;
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} test_vector_t;
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int i =0, j=0;
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// Test vectors
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test_vector_t tests [20];
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initial begin
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$display("Starting fp_mult test...\n");
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// Test cases
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tests[0] = '{32'h3f800000, 32'h40000000, 32'h40000000, "+1.0 * +2.0 = +2.0"};
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tests[1] = '{32'h40400000, 32'h40400000, 32'h41100000, "+3.0 * +3.0 = +9.0"};
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tests[2] = '{32'hc0400000, 32'h40400000, 32'hc1100000, "-3.0 * +3.0 = -9.0"};
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tests[3] = '{32'hbf800000, 32'h40000000, 32'hc0000000, "-1.0 * +2.0 = -2.0"};
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tests[4] = '{32'h3f000000, 32'h3f000000, 32'h3e800000, "+0.5 * +0.5 = +0.25"};
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tests[5] = '{32'h3f800000, 32'h00000000, 32'h00000000, "1.0 * +0.0 = +0.0"};
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tests[6] = '{32'h42280000, 32'hc0e00000, 32'hc3930000, "+42.0 * -7.0 = -294.0"};
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tests[7] = '{32'h414570a4, 32'hb8d1b717, 32'hbaa1be2b, "+12.34 * -0.0001 = -0.001234"};
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tests[8] = '{32'h00000000, 32'h00000000, 32'h00000000, "0.0 * 0.0 = 0.0"};
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tests[9] = '{32'h80000000, 32'h80000000, 32'h00000000, "-0.0 * -0.0 = 0.0"};
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tests[10] = '{32'h00000000, 32'h80000000, 32'h80000000, "0.0 * -0.0 = -0.0"};
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tests[11] = '{32'h3f800000, 32'h80000000, 32'h80000000, "1.0 * -0.0 = -0.0"};
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tests[12] = '{32'h7f800000, 32'h3f800000, 32'h7f800000, "inf * 1.0 = inf"};
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tests[13] = '{32'hff800000, 32'h3f800000, 32'hff800000, "-inf * 1.0 = -inf"};
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tests[14] = '{32'h7f800000, 32'hbf800000, 32'hff800000, "inf * -1.0 = -inf"};
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tests[15] = '{32'hff800000, 32'h7f800000, 32'hff800000, "-inf * inf = -inf"};
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tests[16] = '{32'hff800000, 32'hff800000, 32'h7f800000, "-inf * -inf = +inf"};
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tests[17] = '{32'h00000000, 32'h7f800000, 32'h7f800000, "0.0 * inf = inf"};
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tests[18] = '{32'h80000000, 32'hff800000, 32'h7f800000, "-0.0 * -inf = inf"};
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tests[19] = '{32'h00000000, 32'hff800000, 32'hff800000, "0.0 * -inf = -inf"};
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end
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logic [31:0] z_pipe [2:0];
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always_ff @(negedge clk) begin
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z_pipe[2] <= z_pipe[1];
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z_pipe[1] <= z_pipe[0];
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z_pipe[0] <= z;
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if (i >= 7) begin
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j = i - 7;
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$display("[%0d] %s", j+1, tests[j].desc);
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$display(" A=%h B=%h => Z=%h (expected %h) %s\n",
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tests[j].a, tests[j].b, z_pipe[0], tests[j].expected,
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(z_pipe[0] == tests[j].expected) ? "PASS" : "FAIL");
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end
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a <= tests[i].a;
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b <= tests[i].b;
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i <= i + 1;
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if (i == 19 + 7) $stop;
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end
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endmodule
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