37 lines
912 B
Systemverilog
37 lines
912 B
Systemverilog
//This module is given for the exercises
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module fp_mult_top (
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clk, rst, rnd, a, b, z, status
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);
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input logic [31:0] a, b; // Floating-Point numbers
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input logic [2:0] rnd; // Rounding signal
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output logic [31:0] z; // a ± b
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output logic [7:0] status; // Status Flags
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input logic clk, rst;
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logic [31:0] a1, b1; // Floating-Point numbers
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logic [2:0] rnd1; // Rounding signal
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logic [31:0] z1; // a * b
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logic [7:0] status1; // Status Flags
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fp_mult multiplier(a1,b1,rnd1,z1,status1,clk,rst);
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always @(posedge clk)
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if (!rst)
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begin
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a1 <= '0;
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b1 <= '0;
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rnd1 <= '0;
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z <= '0;
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status <= '0;
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end
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else
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begin
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a1 <= a;
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b1 <= b;
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rnd1 <= rnd;
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z <= z1;
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status <= status1;
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end
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endmodule |