109 lines
3.6 KiB
Systemverilog
109 lines
3.6 KiB
Systemverilog
// sim/fp_mult_tb.sv
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`timescale 1ns/1ps
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module fp_mult_tb;
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logic [31:0] a, b, z;
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logic [2:0] rnd;
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logic [7:0] status;
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logic clk = 0, rst = 0;
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/*
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// DEBUG signals
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logic sign_res_;
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logic [9:0] exp_sum_;
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logic [47:0] mant_prod_;
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logic [22:0] mant_norm_;
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logic [9:0] exp_norm_;
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logic guard_, sticky_;
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logic [24:0] mant_post_rnd_;
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logic [9:0] exp_post_rnd_;
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*/
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// DUT
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fp_mult dut (
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.a(a),
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.b(b),
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.round(rnd),
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.z(z),
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.status(status),
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.clk(clk),
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.rst(rst)
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/*
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// DEBUG signals
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.sign_res_(sign_res_),
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.exp_sum_(exp_sum_),
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.mant_prod_(mant_prod_),
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.mant_norm_(mant_norm_),
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.exp_norm_(exp_norm_),
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.guard_(guard_),
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.sticky_(sticky_),
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.mant_post_rnd_(mant_post_rnd_),
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.exp_post_rnd_(exp_post_rnd_)
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*/
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);
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// Clock generation
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always #5 clk = ~clk;
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typedef struct {
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logic [31:0] a;
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logic [31:0] b;
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logic [31:0] expected;
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string desc;
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} test_vector_t;
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test_vector_t tests [14];
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initial begin
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$display("Starting fp_mult test...\n");
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// Normal multiplication cases
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tests[0] = '{32'h3f800000, 32'h40000000, 32'h40000000, "1.0 * 2.0 = 2.0"};
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tests[1] = '{32'h40400000, 32'h40400000, 32'h41100000, "3.0 * 3.0 = 9.0"};
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tests[2] = '{32'hc0400000, 32'h40400000, 32'hc1100000, "-3.0 * 3.0 = 9.0"};
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tests[3] = '{32'hbf800000, 32'h40000000, 32'hc0000000, "-1.0 * 2.0 = -2.0"};
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tests[4] = '{32'h3f000000, 32'h3f000000, 32'h3e800000, "0.5 * 0.5 = 0.25"};
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tests[5] = '{32'h3f800000, 32'h00000000, 32'h00000000, "1.0 * 0.0 = 0.0"};
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tests[6] = '{32'h42280000, 32'hc0e00000, 32'hc3930000, "42.0 * -7.0 = -294.0"};
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tests[7] = '{32'h414570a4, 32'hb8d1b717, 32'hbaa1be2b, "12.34 * -0.0001 = -0.001234"};
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// Corner cases (some may fail if not handled yet)
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tests[8] = '{32'h00000000, 32'h80000000, 32'h80000000, "0.0 * -0.0 = -0.0"};
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tests[9] = '{32'h3f800000, 32'h80000000, 32'h80000000, "1.0 * -0.0 = -0.0"};
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tests[10] = '{32'h7f800000, 32'h3f800000, 32'h7f800000, "inf * 1.0 = inf"};
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tests[11] = '{32'hff800000, 32'h7f800000, 32'hff800000, "-inf * inf = -inf"};
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tests[12] = '{32'h00000000, 32'h7f800000, 32'h7f800000, "0.0 * inf = inf - nan"};
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tests[13] = '{32'h80000000, 32'hff800000, 32'h7f800000, "-0.0 * -inf = inf - nan"};
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rnd = 3'b000; // default round to nearest
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rst = 1; #10;
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rst = 0; #10;
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for (int i = 0; i < 14; i++) begin
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a = tests[i].a;
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b = tests[i].b;
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#20;
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$display("[%0d] %s", i+1, tests[i].desc);
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/*
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// DEBUG prints
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$display("fp_mult: sign bit = %h", sign_res_);
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$display("fp_mult: exp (pre norm) = %h", exp_sum_);
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$display("fp_mult: mant (pre norm) = %h", mant_prod_);
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$display("fp_mult: exp (norm) = %h", exp_norm_);
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$display("fp_mult: mant (norm) = %h", mant_norm_);
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$display("fp_mult: guard,sticky = %h,%h", guard_,sticky_);
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$display("fp_mult: exp (post rnd) = %h", exp_post_rnd_);
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$display("fp_mult: mant (post rnd) = %h", mant_post_rnd_);
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*/
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$display(" A=%h B=%h => Z=%h (expected %h) %s\n",
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a, b, z, tests[i].expected,
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(z === tests[i].expected) ? "PASS" : "FAIL");
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end
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$display("\nFinished fp_mult test.");
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$stop;
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end
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endmodule
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