`timescale 1ns/1ps module normalize_mult_tb; logic [47:0] mantissa_in; logic [9:0] exponent_in; logic [22:0] mantissa_out; logic [9:0] exponent_out; logic guard_bit, sticky_bit; normalize_mult dut ( .mantissa_in(mantissa_in), .exponent_in(exponent_in), .mantissa_out(mantissa_out), .exponent_out(exponent_out), .guard_bit(guard_bit), .sticky_bit(sticky_bit) ); initial begin integer i; logic [47:0] mantissa_inputs [8]; logic [9:0] exponent_inputs [8]; logic [22:0] exp_mantissas [8]; logic [9:0] exp_exponents [8]; logic exp_guard [8]; logic exp_sticky [8]; string result; $display("Starting normalize_mult test...\n"); mantissa_inputs[0] = 48'hC40000800000; exponent_inputs[0] = 130; exp_mantissas[0] = 23'h440000; exp_exponents[0] = 131; exp_guard[0] = 1; exp_sticky[0] = 0; mantissa_inputs[1] = 48'h440000000080; exponent_inputs[1] = 130; exp_mantissas[1] = 23'h080000; exp_exponents[1] = 130; exp_guard[1] = 0; exp_sticky[1] = 1; mantissa_inputs[2] = 48'h440000400080; exponent_inputs[2] = 130; exp_mantissas[2] = 23'h080000; exp_exponents[2] = 130; exp_guard[2] = 1; exp_sticky[2] = 1; for (i = 0; i < 3; i++) begin mantissa_in = mantissa_inputs[i]; exponent_in = exponent_inputs[i]; #5; if (mantissa_out === exp_mantissas[i] && exponent_out === exp_exponents[i] && guard_bit === exp_guard[i] && sticky_bit === exp_sticky[i]) result = "PASS"; else result = "FAIL"; $display("[%0d] IN=%h | EXP: mant=%h exp=%0d G=%0b S=%0b | OUT: mant=%h exp=%0d G=%0b S=%0b => %s", i, mantissa_inputs[i], exp_mantissas[i], exp_exponents[i], exp_guard[i], exp_sticky[i], mantissa_out, exponent_out, guard_bit, sticky_bit, result ); end $display("\nFinished normalize_mult test."); $stop; end endmodule