121 lines
3.1 KiB
Makefile
121 lines
3.1 KiB
Makefile
#
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# Makefile
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#
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# Copyright (C) 2020 Christos Choutouridis <cchoutou@ece.auth.gr>
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#
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# This program is free software: you can redistribute it and/or modify
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# it under the terms of the GNU Lesser General Public License as
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# published by the Free Software Foundation, either version 3
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# of the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU Lesser General Public License for more details.
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#
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# You should have received a copy of the GNU Lesser General Public License
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# along with this program. If not, see <http://www.gnu.org/licenses/>.
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#
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# ========== Project settings ==========
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TARGET := matmul
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SRC_DIR := src
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INC_DIR :=
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EXC_FILE :=
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# build directories
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BUILD_DIR := bin
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OBJ_DIR := $(BUILD_DIR)/obj
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DEP_DIR := $(BUILD_DIR)/.dep
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# ========== Compiler settings ==========
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CXX := gcc
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CPP := gcc -E
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CSIZE := size
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CFLAGS := -std=gnu99 -Wall -Wextra
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DEB_FLAGS := -DDEBUG -g3
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REL_FLAGS := -O3
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LDFLAGS := -lm
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PRE_DEFS :=
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#
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# =========== Main body and Patterns ===========
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#
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INC := $(foreach dir,$(INC_DIR),-I$(dir))
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DEF := $(foreach def,$(PRE_DEFS),-D$(def))
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# source files
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# recursive search into current and source directories
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SRC := $(wildcard *.c)
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SRC += $(foreach dir,$(SRC_DIR),$(wildcard $(dir)/*.c))
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SRC += $(foreach dir,$(SRC_DIR),$(wildcard $(dir)/**/*.c))
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# exclude every file from the exclude file list
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SRC := $(filter-out $(wildcard $(EXC_FILE)),$(SRC))
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OBJ := $(foreach file,$(SRC:%.c=%.o),$(OBJ_DIR)/$(file))
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DEP := $(foreach file,$(SRC:%.c=%.d),$(DEP_DIR)/$(file))
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# Make Dependencies pattern.
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# This little trick enables recompilation only when dependencies change
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# and it does so for changes both in source AND header files ;)
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#
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# It is based on Tom Tromey's method.
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#
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# Invoke cpp to create makefile rules with dependencies for each source file
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$(DEP_DIR)/%.d: %.c
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@mkdir -p $(@D)
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@$(CPP) $(CFLAGS) $(INC) $(DEF) -MM -MT $(OBJ_DIR)/$(<:.c=.o) -MF $@ $<
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# objects depent on .c AND dependency files, which have an empty recipe
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$(OBJ_DIR)/%.o: %.c $(DEP_DIR)/%.d
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@mkdir -p $(@D)
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$(CXX) -c $(CFLAGS) $(INC) $(DEF) -o $@ $<
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# empty recipe for dependency files. This prevents make errors
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$(DEP):
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# now include all dependencies
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# After all they are makefile dependency rules ;)
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include $(wildcard $(DEP))
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# main target rule
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$(BUILD_DIR)/$(TARGET): $(OBJ)
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@mkdir -p $(@D)
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@echo Linking to target: $(TARGET)
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@echo $(CXX) $(LDFLAGS) -o $(@D)/$(TARGET) '$$(OBJ)'
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@$(CXX) $(LDFLAGS) -o $(@D)/$(TARGET) $(OBJ)
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@echo
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@echo Print size information
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@$(CSIZE) $(@D)/$(TARGET)
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@echo Done
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.PHONY: clean
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clean:
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@echo Cleaning build directories
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@rm -rf $(OBJ_DIR)
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@rm -rf $(DEP_DIR)
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@rm -rf $(BUILD_DIR)
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#
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# ============ User Rules =============
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#
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.PHONY: debug
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debug: CFLAGS += $(DEB_FLAGS)
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debug: $(BUILD_DIR)/$(TARGET)
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.PHONY: release
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release: CFLAGS += $(REL_FLAGS)
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release: clean $(BUILD_DIR)/$(TARGET)
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.PHONY: all
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all: clean release
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